\n

TRGMUX0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMAMUX0

TPM2

FLEXIO0

LPI2C0

LPI2C1

LPI2C2

LPSPI0

LPSPI1

LPSPI2

LPUART0

LPUART1

LPUART2

ADC0

LPIT0

LPCMP0

DAC0

DMAMUX1

LPIT1

TPM3

LPI2C3

LPSPI3

LPUART3

LPCMP1

TPM0

TPM1


DMAMUX0

TRGMUX DMAMUX0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX0 DMAMUX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TPM2

TRGMUX TPM2 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPM2 TPM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


FLEXIO0

TRGMUX FLEXIO0 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLEXIO0 FLEXIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPI2C0

TRGMUX LPI2C0 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPI2C0 LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPI2C1

TRGMUX LPI2C1 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPI2C1 LPI2C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPI2C2

TRGMUX LPI2C2 Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPI2C2 LPI2C2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPSPI0

TRGMUX LPSPI0 Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPSPI0 LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPSPI1

TRGMUX LPSPI1 Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPSPI1 LPSPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPSPI2

TRGMUX LPSPI2 Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPSPI2 LPSPI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPUART0

TRGMUX LPUART0 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPUART0 LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPUART1

TRGMUX LPUART1 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPUART1 LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPUART2

TRGMUX LPUART2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPUART2 LPUART2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


ADC0

TRGMUX ADC0 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC0 ADC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPIT0

TRGMUX LPIT0 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPIT0 LPIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPCMP0

TRGMUX LPCMP0 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPCMP0 LPCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


DAC0

TRGMUX DAC0 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC0 DAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


DMAMUX1

TRGMUX DMAMUX1 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAMUX1 DMAMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPIT1

TRGMUX LPIT1 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPIT1 LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TPM3

TRGMUX TPM3 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPM3 TPM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPI2C3

TRGMUX LPI2C3 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPI2C3 LPI2C3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPSPI3

TRGMUX LPSPI3 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPSPI3 LPSPI3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPUART3

TRGMUX LPUART3 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPUART3 LPUART3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


LPCMP1

TRGMUX LPCMP1 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPCMP1 LPCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TPM0

TRGMUX TPM0 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPM0 TPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.


TPM1

TRGMUX TPM1 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPM1 TPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : TRGMUX register lock.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : UNLOCKED

Register can be written.

0x1 : LOCKED

Register cannot be written until the next system Reset.

End of enumeration elements list.



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