Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Low Power Timer Control Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEN : Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TEN_0
LPTMR is disabled and internal logic is reset.
0x1 : TEN_1
LPTMR is enabled.
End of enumeration elements list.
TMS : Timer Mode Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TMS_0
Time Counter mode.
0x1 : TMS_1
Pulse Counter mode.
End of enumeration elements list.
TFC : Timer Free-Running Counter
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TFC_0
CNR is reset whenever TCF is set.
0x1 : TFC_1
CNR is reset on overflow.
End of enumeration elements list.
TPP : Timer Pin Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TPP_0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
0x1 : TPP_1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
End of enumeration elements list.
TPS : Timer Pin Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TPS_0
Pulse counter input 0 is selected.
0x1 : TPS_1
Pulse counter input 1 is selected.
0x2 : TPS_2
Pulse counter input 2 is selected.
0x3 : TPS_3
Pulse counter input 3 is selected.
End of enumeration elements list.
TIE : Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TIE_0
Timer interrupt disabled.
0x1 : TIE_1
Timer interrupt enabled.
End of enumeration elements list.
TCF : Timer Compare Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TCF_0
The value of CNR is not equal to CMR and increments.
0x1 : TCF_1
The value of CNR is equal to CMR and increments.
End of enumeration elements list.
TDRE : Timer DMA Request Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TDRE_0
Timer DMA Request disabled.
0x1 : TDRE_1
Timer DMA Request enabled.
End of enumeration elements list.
Low Power Timer Prescale Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Prescaler Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : PCS_0
Prescaler/glitch filter clock 0 selected.
0x1 : PCS_1
Prescaler/glitch filter clock 1 selected.
0x2 : PCS_2
Prescaler/glitch filter clock 2 selected.
0x3 : PCS_3
Prescaler/glitch filter clock 3 selected.
End of enumeration elements list.
PBYP : Prescaler Bypass
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : PBYP_0
Prescaler/glitch filter is enabled.
0x1 : PBYP_1
Prescaler/glitch filter is bypassed.
End of enumeration elements list.
PRESCALE : Prescale Value
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : PRESCALE_0
Prescaler divides the prescaler clock by 2 glitch filter does not support this configuration.
0x1 : PRESCALE_1
Prescaler divides the prescaler clock by 4 glitch filter recognizes change on input pin after 2 rising clock edges.
0x2 : PRESCALE_2
Prescaler divides the prescaler clock by 8 glitch filter recognizes change on input pin after 4 rising clock edges.
0x3 : PRESCALE_3
Prescaler divides the prescaler clock by 16 glitch filter recognizes change on input pin after 8 rising clock edges.
0x4 : PRESCALE_4
Prescaler divides the prescaler clock by 32 glitch filter recognizes change on input pin after 16 rising clock edges.
0x5 : PRESCALE_5
Prescaler divides the prescaler clock by 64 glitch filter recognizes change on input pin after 32 rising clock edges.
0x6 : PRESCALE_6
Prescaler divides the prescaler clock by 128 glitch filter recognizes change on input pin after 64 rising clock edges.
0x7 : PRESCALE_7
Prescaler divides the prescaler clock by 256 glitch filter recognizes change on input pin after 128 rising clock edges.
0x8 : PRESCALE_8
Prescaler divides the prescaler clock by 512 glitch filter recognizes change on input pin after 256 rising clock edges.
0x9 : PRESCALE_9
Prescaler divides the prescaler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges.
0xA : PRESCALE_10
Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges.
0xB : PRESCALE_11
Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on input pin after 2048 rising clock edges.
0xC : PRESCALE_12
Prescaler divides the prescaler clock by 8192 glitch filter recognizes change on input pin after 4096 rising clock edges.
0xD : PRESCALE_13
Prescaler divides the prescaler clock by 16,384 glitch filter recognizes change on input pin after 8192 rising clock edges.
0xE : PRESCALE_14
Prescaler divides the prescaler clock by 32,768 glitch filter recognizes change on input pin after 16,384 rising clock edges.
0xF : PRESCALE_15
Prescaler divides the prescaler clock by 65,536 glitch filter recognizes change on input pin after 32,768 rising clock edges.
End of enumeration elements list.
Low Power Timer Compare Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPARE : Compare Value
bits : 0 - 31 (32 bit)
access : read-write
Low Power Timer Counter Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNTER : Counter Value
bits : 0 - 31 (32 bit)
access : read-write
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