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RSIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x130 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

MISC

DSM_TIMER

DSM_CONTROL

DSM_WAKEUP

WOR_DURATION

WOR_WAKE

MAN_SLEEP

MAN_WAKE

RF_OSC_CTRL

ANA_TEST

ANA_TRIM

POWER

SW_CONFIG


CONTROL

Radio System Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_RF_POWER_REQ_EN BLE_RF_POWER_REQ_STAT BLE_RF_POWER_REQ_INT_EN BLE_RF_POWER_REQ_INT RF_OSC_EN RADIO_GASKET_BYPASS_OVRD_EN RADIO_GASKET_BYPASS_OVRD IPP_OBE_BLE_EARLY_WARNING IPP_OBE_RF_ACTIVE IPP_OBE_RF_OSC_EN IPP_OBE_RF_STATUS IPP_OBE_RF_PRIORITY BLE_DSM_EXIT WOR_DSM_EXIT RF_OSC_READY RF_OSC_READY_OVRD_EN RF_OSC_READY_OVRD RSIM_CGC_BLE_EN RSIM_CGC_XCVR_EN RSIM_CGC_ZIG_EN RSIM_CGC_GEN_EN

BLE_RF_POWER_REQ_EN : BLE RF Power Request Enable
bits : 0 - 0 (1 bit)
access : read-write

BLE_RF_POWER_REQ_STAT : BLE RF Power Request Status
bits : 1 - 1 (1 bit)
access : read-only

BLE_RF_POWER_REQ_INT_EN : BLE RF Power Request Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

BLE_RF_POWER_REQ_INT : BLE RF Power Request Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

RF_OSC_EN : RF Ref Osc Enable
bits : 8 - 8 (1 bit)
access : read-write

RADIO_GASKET_BYPASS_OVRD_EN : Radio Gasket Bypass Override Enable
bits : 12 - 12 (1 bit)
access : read-write

RADIO_GASKET_BYPASS_OVRD : Radio Gasket Bypass Override
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : RADIO_GASKET_BYPASS_OVRD_0

XCVR and Link Layer Register Clock is the RF Ref Osc Clock

0x1 : RADIO_GASKET_BYPASS_OVRD_1

XCVR and Link Layer Register Clock is the SoC IPG Clock

End of enumeration elements list.

IPP_OBE_BLE_EARLY_WARNING : IPP_OBE_BLE_EARLY_WARNING
bits : 14 - 14 (1 bit)
access : read-write

IPP_OBE_RF_ACTIVE : IPP_OBE_RF_ACTIVE
bits : 15 - 15 (1 bit)
access : read-write

IPP_OBE_RF_OSC_EN : IPP_OBE_RF_OSC_EN
bits : 16 - 16 (1 bit)
access : read-write

IPP_OBE_RF_STATUS : IPP_OBE_RF_STATUS
bits : 18 - 18 (1 bit)
access : read-write

IPP_OBE_RF_PRIORITY : IPP_OBE_RF_PRIORITY
bits : 19 - 19 (1 bit)
access : read-write

BLE_DSM_EXIT : BLE Force Deep Sleep Mode Exit
bits : 20 - 20 (1 bit)
access : read-write

WOR_DSM_EXIT : Wake on Radio Force Deep Sleep Mode Exit
bits : 21 - 21 (1 bit)
access : read-write

RF_OSC_READY : RF Ref Osc Ready
bits : 24 - 24 (1 bit)
access : read-only

RF_OSC_READY_OVRD_EN : RF Ref Osc Ready Override Enable
bits : 25 - 25 (1 bit)
access : read-write

RF_OSC_READY_OVRD : RF Ref Osc Ready Override
bits : 26 - 26 (1 bit)
access : read-write

RSIM_CGC_BLE_EN : BLE Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : RSIM_CGC_BLE_EN_0

Clock disabled

0x1 : RSIM_CGC_BLE_EN_1

Clock enabled

End of enumeration elements list.

RSIM_CGC_XCVR_EN : XCVR Clock Gate Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : RSIM_CGC_XCVR_EN_0

Clock disabled

0x1 : RSIM_CGC_XCVR_EN_1

Clock enabled

End of enumeration elements list.

RSIM_CGC_ZIG_EN : ZIG Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : RSIM_CGC_ZIG_EN_0

Clock disabled

0x1 : RSIM_CGC_ZIG_EN_1

Clock enabled

End of enumeration elements list.

RSIM_CGC_GEN_EN : GEN Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : RSIM_CGC_GEN_EN_0

Clock disabled

0x1 : RSIM_CGC_GEN_EN_1

Clock enabled

End of enumeration elements list.


MISC

Radio Miscellaneous
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC MISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RADIO_VERSION

RADIO_VERSION : Radio Version ID number
bits : 24 - 31 (8 bit)
access : read-write


DSM_TIMER

Deep Sleep Timer
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSM_TIMER DSM_TIMER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSM_TIMER

DSM_TIMER : Deep Sleep Mode Timer
bits : 0 - 23 (24 bit)
access : read-only


DSM_CONTROL

Deep Sleep Timer Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSM_CONTROL DSM_CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSM_WOR_READY WOR_DEEP_SLEEP_STATUS DSM_WOR_FINISHED WOR_WAKEUP_REQUEST_EN WOR_SLEEP_REQUEST WOR_WAKEUP_REQ WOR_WAKEUP_INTERRUPT_EN WOR_WAKEUP_REQ_INT DSM_MAN_READY MAN_DEEP_SLEEP_STATUS DSM_MAN_FINISHED MAN_WAKEUP_REQUEST_EN MAN_SLEEP_REQUEST MAN_WAKEUP_REQ MAN_WAKEUP_INTERRUPT_EN MAN_WAKEUP_REQ_INT WIFI_COEXIST_1 WIFI_COEXIST_2 WIFI_COEXIST_3 RF_ACTIVE_ENDS_WITH_TSM SW_RF_ACTIVE_ENDS_WITH_TSM SW_RF_ACTIVE_BIT SW_RF_ACTIVE_EN DSM_TIMER_CLR DSM_TIMER_EN

DSM_WOR_READY : WOR Ready for Deep Sleep Mode
bits : 0 - 0 (1 bit)
access : read-only

WOR_DEEP_SLEEP_STATUS : WOR Deep Sleep Mode Status
bits : 1 - 1 (1 bit)
access : read-only

DSM_WOR_FINISHED : WOR Deep Sleep Time Finished
bits : 2 - 2 (1 bit)
access : read-only

WOR_WAKEUP_REQUEST_EN : Enable WOR Deep Sleep Module to initiate a Radio Wakeup
bits : 3 - 3 (1 bit)
access : read-write

WOR_SLEEP_REQUEST : WOR Deep Sleep Requested
bits : 4 - 4 (1 bit)
access : read-only

WOR_WAKEUP_REQ : WOR Deep Sleep Module Radio Wakeup Status
bits : 5 - 5 (1 bit)
access : read-only

WOR_WAKEUP_INTERRUPT_EN : WOR Deep Sleep Module Radio Wakeup Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

WOR_WAKEUP_REQ_INT : Interrupt Flag from an WOR Deep Sleep Module Radio Wakeup
bits : 7 - 7 (1 bit)
access : read-write

DSM_MAN_READY : MAN Ready for Deep Sleep Mode
bits : 8 - 8 (1 bit)
access : read-only

MAN_DEEP_SLEEP_STATUS : MAN Deep Sleep Mode Status
bits : 9 - 9 (1 bit)
access : read-only

DSM_MAN_FINISHED : MAN Deep Sleep Time Finished
bits : 10 - 10 (1 bit)
access : read-only

MAN_WAKEUP_REQUEST_EN : Enable MAN Deep Sleep Module to initiate a Radio Wakeup
bits : 11 - 11 (1 bit)
access : read-write

MAN_SLEEP_REQUEST : MAN Deep Sleep Requested
bits : 12 - 12 (1 bit)
access : read-only

MAN_WAKEUP_REQ : MAN Deep Sleep Module Radio Wakeup Status
bits : 13 - 13 (1 bit)
access : read-only

MAN_WAKEUP_INTERRUPT_EN : MAN Deep Sleep Module Radio Wakeup Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

MAN_WAKEUP_REQ_INT : Interrupt Flag from an MAN Deep Sleep Module Radio Wakeup
bits : 15 - 15 (1 bit)
access : read-write

WIFI_COEXIST_1 : RF_ACTIVE Source
bits : 16 - 16 (1 bit)
access : read-only

WIFI_COEXIST_2 : RF_STATUS Source
bits : 17 - 17 (1 bit)
access : read-only

WIFI_COEXIST_3 : RF_EARLY_WARNING Source
bits : 18 - 18 (1 bit)
access : read-only

RF_ACTIVE_ENDS_WITH_TSM : RF_ACTIVE clearing mechanism
bits : 20 - 20 (1 bit)
access : read-only

SW_RF_ACTIVE_ENDS_WITH_TSM : Software RF_ACTIVE clearing mechanism
bits : 21 - 21 (1 bit)
access : read-only

SW_RF_ACTIVE_BIT : Software RF_ACTIVE Control Bit
bits : 22 - 22 (1 bit)
access : read-write

SW_RF_ACTIVE_EN : Software RF_ACTIVE Control Enable
bits : 23 - 23 (1 bit)
access : read-only

DSM_TIMER_CLR : Deep Sleep Mode Timer Clear
bits : 27 - 27 (1 bit)
access : read-write

DSM_TIMER_EN : Deep Sleep Mode Timer Enable
bits : 31 - 31 (1 bit)
access : read-write


DSM_WAKEUP

Deep Sleep Wakeup Sequence
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSM_WAKEUP DSM_WAKEUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSM_POWER_OFFSET_TIME ACTIVE_WARNING FINE_DELAY COARSE_DELAY

DSM_POWER_OFFSET_TIME : Deep Sleep Wakeup Power Offset Time
bits : 0 - 9 (10 bit)
access : read-write

ACTIVE_WARNING : Deep Sleep Wakeup RF Active Warning Time
bits : 12 - 17 (6 bit)
access : read-write

FINE_DELAY : Deep Sleep Wakeup Fine Delay Time
bits : 20 - 25 (6 bit)
access : read-write

COARSE_DELAY : Deep Sleep Wakeup Coarse Delay Time
bits : 28 - 31 (4 bit)
access : read-write


WOR_DURATION

WOR Deep Sleep Duration
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WOR_DURATION WOR_DURATION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WOR_DSM_DURATION

WOR_DSM_DURATION : WOR Deep Sleep Time Elapsed
bits : 0 - 23 (24 bit)
access : read-only


WOR_WAKE

WOR Deep Sleep Wake Time
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WOR_WAKE WOR_WAKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WOR_WAKE_TIME WOR_FSM_STATE

WOR_WAKE_TIME : WOR Deep Sleep Module Wake Time
bits : 0 - 23 (24 bit)
access : read-write

WOR_FSM_STATE : WOR Deep Sleep State Machine State
bits : 28 - 30 (3 bit)
access : read-only


MAN_SLEEP

MAN Deep Sleep Time
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAN_SLEEP MAN_SLEEP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAN_SLEEP_TIME

MAN_SLEEP_TIME : MAN Deep Sleep Module Sleep Time
bits : 0 - 23 (24 bit)
access : read-write


MAN_WAKE

MAN Deep Sleep Wake Time
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAN_WAKE MAN_WAKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAN_WAKE_TIME MAN_FSM_STATE

MAN_WAKE_TIME : MAN Deep Sleep Module Wake Time
bits : 0 - 23 (24 bit)
access : read-write

MAN_FSM_STATE : MAN Deep Sleep State Machine State
bits : 28 - 30 (3 bit)
access : read-only


RF_OSC_CTRL

Radio Oscillator Control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RF_OSC_CTRL RF_OSC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BB_XTAL_ALC_COUNT_SEL BB_XTAL_ALC_ON RF_OSC_BYPASS_EN BB_XTAL_COMP_BIAS BB_XTAL_DC_COUP_MODE_EN BB_XTAL_DIAGSEL BB_XTAL_DIG_CLK_ON BB_XTAL_GM BB_XTAL_ON_OVRD BB_XTAL_ON_OVRD_ON BB_XTAL_READY_COUNT_SEL RADIO_EXT_OSC_RF_EN_SEL RADIO_EXT_OSC_OVRD RADIO_EXT_OSC_OVRD_EN RF_NOT_ALLOWED_OVRD RF_NOT_ALLOWED_OVRD_EN

BB_XTAL_ALC_COUNT_SEL : rmap_bb_xtal_alc_count_sel_hv[1:0]
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : BB_XTAL_ALC_COUNT_SEL_0

2048 (64 us @ 32 MHz)

0x1 : BB_XTAL_ALC_COUNT_SEL_1

4096 (128 us @ 32 MHz)

0x2 : BB_XTAL_ALC_COUNT_SEL_2

8192 (256 us @ 32 MHz)

0x3 : BB_XTAL_ALC_COUNT_SEL_3

16384 (512 us @ 32 MHz)

End of enumeration elements list.

BB_XTAL_ALC_ON : rmap_bb_xtal_alc_on_hv
bits : 2 - 2 (1 bit)
access : read-write

RF_OSC_BYPASS_EN : RF Ref Osc Bypass Enable
bits : 3 - 3 (1 bit)
access : read-write

BB_XTAL_COMP_BIAS : rmap_bb_xtal_comp_bias_hv[4:0]
bits : 4 - 8 (5 bit)
access : read-write

BB_XTAL_DC_COUP_MODE_EN : rmap_bb_xtal_dc_coup_mode_en_hv
bits : 9 - 9 (1 bit)
access : read-write

BB_XTAL_DIAGSEL : rmap_bb_xtal_diagsel_hv
bits : 10 - 10 (1 bit)
access : read-write

BB_XTAL_DIG_CLK_ON : rmap_bb_xtal_dig_clk_on_hv
bits : 11 - 11 (1 bit)
access : read-write

BB_XTAL_GM : rmap_bb_xtal_gm_hv[4:0]
bits : 12 - 16 (5 bit)
access : read-write

BB_XTAL_ON_OVRD : rmap_bb_xtal_on_ovrd_hv
bits : 17 - 17 (1 bit)
access : read-write

BB_XTAL_ON_OVRD_ON : rmap_bb_xtal_on_ovrd_on_hv
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : BB_XTAL_ON_OVRD_ON_0

rfctrl_bb_xtal_on_hv is asserted

0x1 : BB_XTAL_ON_OVRD_ON_1

rfctrl_bb_xtal_on_ovrd_hv is asserted

End of enumeration elements list.

BB_XTAL_READY_COUNT_SEL : rmap_bb_xtal_ready_count_sel_hv[1:0]
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : BB_XTAL_READY_COUNT_SEL_0

1024 counts (32 us @ 32 MHz)

0x1 : BB_XTAL_READY_COUNT_SEL_1

2048 (64 us @ 32 MHz)

0x2 : BB_XTAL_READY_COUNT_SEL_2

4096 (128 us @ 32 MHz)

0x3 : BB_XTAL_READY_COUNT_SEL_3

8192 (256 us @ 32 MHz)

End of enumeration elements list.

RADIO_EXT_OSC_RF_EN_SEL : Radio External Request for RF OSC Select
bits : 27 - 27 (1 bit)
access : read-write

RADIO_EXT_OSC_OVRD : Radio External Request for RF OSC Override
bits : 28 - 28 (1 bit)
access : read-write

RADIO_EXT_OSC_OVRD_EN : Radio External Request for RF OSC Override Enable
bits : 29 - 29 (1 bit)
access : read-write

RF_NOT_ALLOWED_OVRD : RF Not Allowed Override
bits : 30 - 30 (1 bit)
access : read-write

RF_NOT_ALLOWED_OVRD_EN : RF Not Allowed Override Enable
bits : 31 - 31 (1 bit)
access : read-write


ANA_TEST

Radio Analog Test Registers
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA_TEST ANA_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_OUT_BUF_EN

XTAL_OUT_BUF_EN : XTAL Output Buffer Enable
bits : 4 - 4 (1 bit)
access : read-write


ANA_TRIM

Radio Analog Trim Registers
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA_TRIM ANA_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BB_LDO_LS_SPARE BB_LDO_LS_TRIM BB_LDO_XO_SPARE BB_LDO_XO_TRIM BB_XTAL_SPARE BB_XTAL_TRIM BG_1V_TRIM BG_IBIAS_5U_TRIM

BB_LDO_LS_SPARE : rmap_bb_ldo_ls_spare_hv[1:0]
bits : 0 - 1 (2 bit)
access : read-write

BB_LDO_LS_TRIM : rmap_bb_ldo_ls_trim_hv[2:0]
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : BB_LDO_LS_TRIM_0

1.20 V (Default)

0x1 : BB_LDO_LS_TRIM_1

1.25 V

0x2 : BB_LDO_LS_TRIM_2

1.28 V

0x3 : BB_LDO_LS_TRIM_3

1.33 V

0x4 : BB_LDO_LS_TRIM_4

1.40 V

0x5 : BB_LDO_LS_TRIM_5

1.44 V

0x6 : BB_LDO_LS_TRIM_6

1.50 V

0x7 : BB_LDO_LS_TRIM_7

1.66 V

End of enumeration elements list.

BB_LDO_XO_SPARE : rmap_bb_ldo_xo_spare_hv[1:0]
bits : 6 - 7 (2 bit)
access : read-write

BB_LDO_XO_TRIM : rmap_bb_ldo_xo_trim_hv[2:0]
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : BB_LDO_XO_TRIM_0

1.20 V (Default)

0x1 : BB_LDO_XO_TRIM_1

1.25 V

0x2 : BB_LDO_XO_TRIM_2

1.28 V

0x3 : BB_LDO_XO_TRIM_3

1.33 V

0x4 : BB_LDO_XO_TRIM_4

1.40 V

0x5 : BB_LDO_XO_TRIM_5

1.44 V

0x6 : BB_LDO_XO_TRIM_6

1.50 V

0x7 : BB_LDO_XO_TRIM_7

1.66 V

End of enumeration elements list.

BB_XTAL_SPARE : rmap_bb_xtal_spare_hv[4:0]
bits : 11 - 15 (5 bit)
access : read-write

BB_XTAL_TRIM : rmap_bb_xtal_trim_hv[7:0]
bits : 16 - 23 (8 bit)
access : read-write

BG_1V_TRIM : rmap_bg_1v_trim_hv[3:0]
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0 : BG_1V_TRIM_0

954.14 mV

0x1 : BG_1V_TRIM_1

959.26 mV

0x2 : BG_1V_TRIM_2

964.38 mV

0x3 : BG_1V_TRIM_3

969.5 mV

0x4 : BG_1V_TRIM_4

974.6 mV

0x5 : BG_1V_TRIM_5

979.7 mV

0x6 : BG_1V_TRIM_6

984.8 mV

0x7 : BG_1V_TRIM_7

989.9 mV

0x8 : BG_1V_TRIM_8

995 mV (Default)

0x9 : BG_1V_TRIM_9

1 V

0xA : BG_1V_TRIM_10

1.005 V

0xB : BG_1V_TRIM_11

1.01 V

0xC : BG_1V_TRIM_12

1.015 V

0xD : BG_1V_TRIM_13

1.02 V

0xE : BG_1V_TRIM_14

1.025 V

0xF : BG_1V_TRIM_15

1.031 V

End of enumeration elements list.

BG_IBIAS_5U_TRIM : rmap_bg_ibias_5u_trim_hv[3:0]
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

0 : BG_IBIAS_5U_TRIM_0

3.55 uA

0x1 : BG_IBIAS_5U_TRIM_1

3.73 uA

0x2 : BG_IBIAS_5U_TRIM_2

4.04 uA

0x3 : BG_IBIAS_5U_TRIM_3

4.22 uA

0x4 : BG_IBIAS_5U_TRIM_4

4.39 uA

0x5 : BG_IBIAS_5U_TRIM_5

4.57 uA

0x6 : BG_IBIAS_5U_TRIM_6

4.89 uA

0x7 : BG_IBIAS_5U_TRIM_7

5.06 (Default)

0x8 : BG_IBIAS_5U_TRIM_8

5.23 uA

0x9 : BG_IBIAS_5U_TRIM_9

5.41 uA

0xA : BG_IBIAS_5U_TRIM_10

5.72 uA

0xB : BG_IBIAS_5U_TRIM_11

5.9 uA

0xC : BG_IBIAS_5U_TRIM_12

6.07 uA

0xD : BG_IBIAS_5U_TRIM_13

6.25 uA

0xE : BG_IBIAS_5U_TRIM_14

6.56 uA

0xF : BG_IBIAS_5U_TRIM_15

6.74 uA

End of enumeration elements list.


POWER

RSIM Power Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RADIO_STOP_MODE_STAT SPM_STOP_ACK_STAT RADIO_STOP_MODE_OVRD RADIO_STOP_MODE_OVRD_EN RADIO_STOP_ACK_STAT RADIO_STOP_REQ_STAT RSIM_STOP_REQ_OVRD RSIM_STOP_REQ_OVRD_EN RF_OSC_EN_OVRD RF_OSC_EN_OVRD_EN RF_POWER_EN_OVRD RF_POWER_EN_OVRD_EN SPM_ISO_STAT RADIO_ISO_STAT RSIM_ISO_OVRD RSIM_ISO_OVRD_EN SPM_RUN_ACK_STAT RADIO_RUN_REQ_STAT RSIM_RUN_REQ_OVRD RSIM_RUN_REQ_OVRD_EN SPM_STOP_REQ_ACK_OVRD SPM_STOP_REQ_ACK_OVRD_EN SPM_RUN_REQ_ACK_OVRD SPM_RUN_REQ_ACK_OVRD_EN RSIM_STOP_MODE RSIM_RUN_REQUEST

RADIO_STOP_MODE_STAT : Radio Stop Mode Status
bits : 0 - 2 (3 bit)
access : read-only

SPM_STOP_ACK_STAT : SPM Stop Acknowledge Status
bits : 3 - 3 (1 bit)
access : read-only

RADIO_STOP_MODE_OVRD : Radio Stop Mode Override
bits : 4 - 6 (3 bit)
access : read-write

RADIO_STOP_MODE_OVRD_EN : Radio Stop Mode Override Enable
bits : 7 - 7 (1 bit)
access : read-write

RADIO_STOP_ACK_STAT : Radio Stop Acknowledge Status
bits : 8 - 8 (1 bit)
access : read-only

RADIO_STOP_REQ_STAT : Radio Stop Request Status
bits : 9 - 9 (1 bit)
access : read-only

RSIM_STOP_REQ_OVRD : Radio Stop Request Override
bits : 10 - 10 (1 bit)
access : read-write

RSIM_STOP_REQ_OVRD_EN : Radio Stop Request Override Enable
bits : 11 - 11 (1 bit)
access : read-write

RF_OSC_EN_OVRD : Radio Osc Enable Override
bits : 12 - 12 (1 bit)
access : read-write

RF_OSC_EN_OVRD_EN : Radio Osc Enable Override Enable
bits : 13 - 13 (1 bit)
access : read-write

RF_POWER_EN_OVRD : Radio Power Enable Override
bits : 14 - 14 (1 bit)
access : read-write

RF_POWER_EN_OVRD_EN : Radio Power Enable Override Enable
bits : 15 - 15 (1 bit)
access : read-write

SPM_ISO_STAT : SPM ISO Status
bits : 16 - 16 (1 bit)
access : read-only

RADIO_ISO_STAT : Radio Isolation Status
bits : 17 - 17 (1 bit)
access : read-only

RSIM_ISO_OVRD : RSIM ISO Override
bits : 18 - 18 (1 bit)
access : read-write

RSIM_ISO_OVRD_EN : RSIM ISO Override Enable
bits : 19 - 19 (1 bit)
access : read-write

SPM_RUN_ACK_STAT : SPM Run Request Acknowledge Status
bits : 20 - 20 (1 bit)
access : read-only

RADIO_RUN_REQ_STAT : Radio Run Request Status
bits : 21 - 21 (1 bit)
access : read-only

RSIM_RUN_REQ_OVRD : RSIM Run Request Override
bits : 22 - 22 (1 bit)
access : read-write

RSIM_RUN_REQ_OVRD_EN : RSIM Run Request Override Enable
bits : 23 - 23 (1 bit)
access : read-write

SPM_STOP_REQ_ACK_OVRD : SPM Stop Request Acknowledge Override
bits : 24 - 24 (1 bit)
access : read-write

SPM_STOP_REQ_ACK_OVRD_EN : SPM Stop Request Acknowledge Override Enable
bits : 25 - 25 (1 bit)
access : read-write

SPM_RUN_REQ_ACK_OVRD : SPM Run Request Acknowledge Override
bits : 26 - 26 (1 bit)
access : read-write

SPM_RUN_REQ_ACK_OVRD_EN : SPM Run Request Acknowledge Override Enable
bits : 27 - 27 (1 bit)
access : read-write

RSIM_STOP_MODE : RSIM lowest allowed Stop Mode
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

0x3 : RSIM_STOP_MODE_3

RLLS mode (Radio State Retention mode)

0x7 : RSIM_STOP_MODE_7

RVLLS mode (This is the POR setting)

End of enumeration elements list.

RSIM_RUN_REQUEST : RSIM Run Regulator Request
bits : 31 - 31 (1 bit)
access : read-write


SW_CONFIG

Radio Software Configuration
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_CONFIG SW_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RADIO_CONFIGURED_POR_RESET RADIO_CONFIGURED_SYS_RESET RSIM_RF_ACTIVE_OVRD RSIM_RF_ACTIVE_OVRD_EN RADIO_POR_BIT RSIM_RADIO_ISO_POR_OVRD RADIO_RESET_BIT WAKEUP_INTERRUPT_SOURCE RADIO0_INTERRUPT_EN RADIO1_INTERRUPT_EN BLOCK_SOC_RESETS BLOCK_RADIO_OUTPUTS ALLOW_DFT_RESETS BLOCK_EXT_OSC_PWR_REQ

RADIO_CONFIGURED_POR_RESET : Radio Configuration Bit, cleared by Radio Power On Reset
bits : 0 - 0 (1 bit)
access : read-write

RADIO_CONFIGURED_SYS_RESET : Radio Configuration Bit, cleared by Radio System Reset
bits : 1 - 1 (1 bit)
access : read-write

RSIM_RF_ACTIVE_OVRD : RF Active Internal Override
bits : 4 - 4 (1 bit)
access : read-write

RSIM_RF_ACTIVE_OVRD_EN : RF Active Internal Override Enable
bits : 5 - 5 (1 bit)
access : read-write

RADIO_POR_BIT : Software Power On Reset for the Radio
bits : 8 - 8 (1 bit)
access : read-write

RSIM_RADIO_ISO_POR_OVRD : RSIM ISO_POR Override
bits : 12 - 12 (1 bit)
access : read-write

RADIO_RESET_BIT : Software System Reset for the Radio
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_INTERRUPT_SOURCE : RSIM Wakeup Interrupt Source Selector
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : WAKEUP_INTERRUPT_SOURCE_0

No Radio Power-On Sequence interrupt will be generated.

0x1 : WAKEUP_INTERRUPT_SOURCE_1

A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC.

0x2 : WAKEUP_INTERRUPT_SOURCE_2

A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source.

0x3 : WAKEUP_INTERRUPT_SOURCE_3

A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs

End of enumeration elements list.

RADIO0_INTERRUPT_EN : Radio0 Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

RADIO1_INTERRUPT_EN : Radio1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write

BLOCK_SOC_RESETS : Block SoC Resets of the Radio, cleared by Radio System Reset
bits : 28 - 28 (1 bit)
access : read-write

BLOCK_RADIO_OUTPUTS : Block Radio Outputs
bits : 29 - 29 (1 bit)
access : read-write

ALLOW_DFT_RESETS : Allow the DFT Reset Pin to Reset the Radio
bits : 30 - 30 (1 bit)
access : read-write

BLOCK_EXT_OSC_PWR_REQ : Block External Requests for RF OSC from starting a Radio Power Wakeup Sequence
bits : 31 - 31 (1 bit)
access : read-write



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