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WWDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

MOD

WARNINT

WINDOW

TC

FEED

TV


MOD

Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDEN WDRESET WDTOF WDINT WDPROTECT RESERVED

WDEN : Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : STOP

The watchdog timer is stopped.

1 : RUN

The watchdog timer is running.

End of enumeration elements list.

WDRESET : Watchdog reset enable bit. This bit is Set Only.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : INTERRUPT

A watchdog timeout will not cause a chip reset.

1 : RESET

A watchdog timeout will cause a chip reset.

End of enumeration elements list.

WDTOF : Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.
bits : 2 - 4 (3 bit)

WDINT : Watchdog interrupt flag. Set when the timer reaches the value in WARNINT. Cleared by software.
bits : 3 - 6 (4 bit)

WDPROTECT : Watchdog update mode. This bit is Set Only.
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : UPDATE

The watchdog reload value (TC) can be changed at any time.

1 : BLOCKED

The watchdog reload value (TC) can be changed only after the counter is below the value of WARNINT and WINDOW. Note: this mode is intended for use only when WDRESET =1.

End of enumeration elements list.

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 5 - 36 (32 bit)


WARNINT

Watchdog Warning Interrupt compare value.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WARNINT WARNINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPVAL RESERVED

COMPVAL : Watchdog warning interrupt compare value.
bits : 0 - 9 (10 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 41 (32 bit)


WINDOW

Watchdog Window compare value.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINDOW WINDOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINVAL RESERVED

WINVAL : Watchdog window value.
bits : 0 - 23 (24 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)


TC

Watchdog timer constant register. This register determines the time-out value.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RESERVED

COUNT : Watchdog time-out interval.
bits : 0 - 23 (24 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)


FEED

Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FEED FEED write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEEDVAL RESERVED

FEEDVAL : Feed value should be 0xAA followed by 0x55.
bits : 0 - 7 (8 bit)

RESERVED : Reserved
bits : 8 - 39 (32 bit)


TV

Watchdog timer value register. This register reads out the current value of the Watchdog timer.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TV TV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RESERVED

COUNT : Counter timer value.
bits : 0 - 23 (24 bit)

RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)



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