\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Control Register 0. Selects the serial clock rate, bus type, and data size.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSS : Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
bits : 0 - 3 (4 bit)
Enumeration: ENUM
0x3 : 4_BIT_TRANSFER
4-bit transfer
0x4 : 5_BIT_TRANSFER
5-bit transfer
0x5 : 6_BIT_TRANSFER
6-bit transfer
0x6 : 7_BIT_TRANSFER
7-bit transfer
0x7 : 8_BIT_TRANSFER
8-bit transfer
0x8 : 9_BIT_TRANSFER
9-bit transfer
0x9 : 10_BIT_TRANSFER
10-bit transfer
0xA : 11_BIT_TRANSFER
11-bit transfer
0xB : 12_BIT_TRANSFER
12-bit transfer
0xC : 13_BIT_TRANSFER
13-bit transfer
0xD : 14_BIT_TRANSFER
14-bit transfer
0xE : 15_BIT_TRANSFER
15-bit transfer
0xF : 16_BIT_TRANSFER
16-bit transfer
End of enumeration elements list.
FRF : Frame Format.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : SPI
SPI
0x1 : TI
TI
0x2 : MICROWIRE
Microwire
0x3 : RESERVED
This combination is not supported and should not be used.
End of enumeration elements list.
CPOL : Clock Out Polarity. This bit is only used in SPI mode.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : LOW
SPI controller maintains the bus clock low between frames.
1 : HIGH
SPI controller maintains the bus clock high between frames.
End of enumeration elements list.
CPHA : Clock Out Phase. This bit is only used in SPI mode.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : FIRSTCLOCK
SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.
1 : SECONDCLOCK
SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.
End of enumeration elements list.
SCR : Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).
bits : 8 - 23 (16 bit)
RESERVED : Reserved
bits : 16 - 47 (32 bit)
Clock Prescale Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPSDVSR : This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
bits : 0 - 7 (8 bit)
RESERVED : Reserved.
bits : 8 - 39 (32 bit)
Interrupt Mask Set and Clear Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIM : Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bits : 0 - 0 (1 bit)
RTIM : Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)
RXIM : Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
bits : 2 - 4 (3 bit)
TXIM : Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
bits : 3 - 6 (4 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Raw Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORRIS : This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
bits : 0 - 0 (1 bit)
RTRIS : This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)
RXRIS : This bit is 1 if the Rx FIFO is at least half full.
bits : 2 - 4 (3 bit)
TXRIS : This bit is 1 if the Tx FIFO is at least half empty.
bits : 3 - 6 (4 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Masked Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORMIS : This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
bits : 0 - 0 (1 bit)
RTMIS : This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)
RXMIS : This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
bits : 2 - 4 (3 bit)
TXMIS : This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
bits : 3 - 6 (4 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
SSPICR Interrupt Clear Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RORIC : Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
bits : 0 - 0 (1 bit)
RTIC : Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
bits : 1 - 2 (2 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 2 - 33 (32 bit)
Control Register 1. Selects master/slave and other modes.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBM : Loop Back Mode.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DURING_NORMAL_OPERAT
During normal operation.
1 : SERIAL_INPUT_IS_TAKE
Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
End of enumeration elements list.
SSE : SPI Enable.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
The SPI controller is disabled.
1 : ENABLED
The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit.
End of enumeration elements list.
MS : Master/Slave Mode.This bit can only be written when the SSE bit is 0.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : MASTER
The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
1 : SLAVE
The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.
End of enumeration elements list.
SOD : Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).
bits : 3 - 6 (4 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.
bits : 0 - 15 (16 bit)
RESERVED : Reserved.
bits : 16 - 47 (32 bit)
Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFE : Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
bits : 0 - 0 (1 bit)
TNF : Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
bits : 1 - 2 (2 bit)
RNE : Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
bits : 2 - 4 (3 bit)
RFF : Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
bits : 3 - 6 (4 bit)
BSY : Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
bits : 4 - 8 (5 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 5 - 36 (32 bit)
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