Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)
address_offset : 0x0 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
THR : Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1)
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
alternate_register : RBR
reset_Mask : 0x0
DLLSB : The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Modem control register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRCTRL : Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active.
bits : 0 - 0 (1 bit)
RTSCTRL : Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
bits : 1 - 2 (2 bit)
LMS : Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.
bits : 4 - 8 (5 bit)
Enumeration: test
0 : DISABLE_MODEM_LOOPBA
Disable modem loopback mode.
1 : ENABLE_MODEM_LOOPBAC
Enable modem loopback mode.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 5 - 10 (6 bit)
RTSEN : RTS enable
bits : 6 - 12 (7 bit)
Enumeration: test
0 : DISABLE_AUTO_RTS_FLO
Disable auto-rts flow control.
1 : ENABLE_AUTO_RTS_FLOW
Enable auto-rts flow control.
End of enumeration elements list.
CTSEN : CTS enable
bits : 7 - 14 (8 bit)
Enumeration: test
0 : DISABLE_AUTO_CTS_FLO
Disable auto-cts flow control.
1 : ENABLE_AUTO_CTS_FLOW
Enable auto-cts flow control.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Line Status Register. Contains flags for transmit and receive status, including line errors.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.
bits : 0 - 0 (1 bit)
Enumeration: test
0 : RBR_IS_EMPTY_
RBR is empty.
1 : RBR_CONTAINS_VALID_D
RBR contains valid data.
End of enumeration elements list.
OE : Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
bits : 1 - 2 (2 bit)
Enumeration: test
0 : INACTIVE
Overrun error status is inactive.
1 : ACTIVE
Overrun error status is active.
End of enumeration elements list.
PE : Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
bits : 2 - 4 (3 bit)
Enumeration: test
0 : INACTIVE
Parity error status is inactive.
1 : ACTIVE
Parity error status is active.
End of enumeration elements list.
FE : Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
bits : 3 - 6 (4 bit)
Enumeration: test
0 : INACTIVE
Framing error status is inactive.
1 : ACTIVE
Framing error status is active.
End of enumeration elements list.
BI : Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
bits : 4 - 8 (5 bit)
Enumeration: test
0 : INACTIVE
Break interrupt status is inactive.
1 : ACTIVE
Break interrupt status is active.
End of enumeration elements list.
THRE : Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.
bits : 5 - 10 (6 bit)
Enumeration: test
0 : THR_CONTAINS_VALID_D
THR contains valid data.
1 : THR_IS_EMPTY_
THR is empty.
End of enumeration elements list.
TEMT : Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data.
bits : 6 - 12 (7 bit)
Enumeration: test
0 : VALID_DATA
THR and/or the TSR contains valid data.
1 : EMPTY
THR and the TSR are empty.
End of enumeration elements list.
RXFE : Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.
bits : 7 - 14 (8 bit)
Enumeration: test
0 : RBR_CONTAINS_NO_UART
RBR contains no UART RX errors or FCR[0]=0.
1 : UART_RBR_CONTAINS_AT
UART RBR contains at least one UART RX error.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Modem status register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCTS : Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.
bits : 0 - 0 (1 bit)
Enumeration: test
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, CTS.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, CTS.
End of enumeration elements list.
DDSR : Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.
bits : 1 - 2 (2 bit)
Enumeration: test
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, DSR.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, DSR.
End of enumeration elements list.
TERI : Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.
bits : 2 - 4 (3 bit)
Enumeration: test
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, RI.
1 : LOW_TO_HIGH_TRANSITI
Low-to-high transition detected on RI.
End of enumeration elements list.
DDCD : Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.
bits : 3 - 6 (4 bit)
Enumeration: test
0 : NO_CHANGE_DETECTED_O
No change detected on modem input, DCD.
1 : STATE_CHANGE_DETECTE
State change detected on modem input, DCD.
End of enumeration elements list.
CTS : Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.
bits : 4 - 8 (5 bit)
DSR : Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
bits : 5 - 10 (6 bit)
RI : Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.
bits : 6 - 12 (7 bit)
DCD : Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.
bits : 7 - 14 (8 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Scratch Pad Register. Eight-bit temporary storage for software.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAD : A readable, writable byte.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Auto-baud Control Register. Contains controls for the auto-baud feature.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start bit. This bit is automatically cleared after auto-baud completion.
bits : 0 - 0 (1 bit)
Enumeration: test
0 : AUTO_BAUD_STOP_(AUTO
Auto-baud stop (auto-baud is not running).
1 : AUTO_BAUD_START_(AUT
Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
End of enumeration elements list.
MODE : Auto-baud mode select bit.
bits : 1 - 2 (2 bit)
Enumeration: test
0 : MODE_0_
Mode 0.
1 : MODE_1_
Mode 1.
End of enumeration elements list.
AUTORESTART : Start mode.
bits : 2 - 4 (3 bit)
Enumeration: test
0 : NO_RESTART
No restart
1 : RESTART_IN_CASE_OF_T
Restart in case of time-out (counter restarts at next UART RX falling edge)
End of enumeration elements list.
ABEOINTCLR : End of auto-baud interrupt clear bit (write only accessible).
bits : 8 - 16 (9 bit)
Enumeration: test
0 : WRITING_A_0_HAS_NO_I
Writing a 0 has no impact.
1 : CLEAR
Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
ABTOINTCLR : Auto-baud time-out interrupt clear bit (write only accessible).
bits : 9 - 18 (10 bit)
Enumeration: test
0 : WRITING_A_0_HAS_NO_I
Writing a 0 has no impact.
1 : CLEAR
Writing a 1 will clear the corresponding interrupt in the IIR.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
Fractional Divider Register. Generates a clock input for the baud rate divider.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVADDVAL : Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
bits : 0 - 3 (4 bit)
MULVAL : Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.
bits : 4 - 11 (8 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
Transmit Enable Register. Turns off UART transmitter for use with software flow control.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEN : When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.
bits : 7 - 14 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLMSB : The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : DLM
reset_Mask : 0x0
RBRIE : RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt.
bits : 0 - 0 (1 bit)
Enumeration: test
0 : DISABLE_THE_RDA_INTE
Disable the RDA interrupts.
1 : ENABLE_THE_RDA_INTER
Enable the RDA interrupts.
End of enumeration elements list.
THREIE : THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5].
bits : 1 - 2 (2 bit)
Enumeration: test
0 : DISABLE_THE_THRE_INT
Disable the THRE interrupts.
1 : ENABLE_THE_THRE_INTE
Enable the THRE interrupts.
End of enumeration elements list.
RXLIE : RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].
bits : 2 - 4 (3 bit)
Enumeration: test
0 : DISABLE_THE_RX_LINE_
Disable the RX line status interrupts.
1 : ENABLE_THE_RX_LINE_S
Enable the RX line status interrupts.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 4 - 10 (7 bit)
RESERVED : Reserved
bits : 7 - 14 (8 bit)
ABEOINTEN : Enables the end of auto-baud interrupt.
bits : 8 - 16 (9 bit)
Enumeration: test
0 : DISABLE_END_OF_AUTO_
Disable end of auto-baud Interrupt.
1 : ENABLE_END_OF_AUTO_B
Enable end of auto-baud Interrupt.
End of enumeration elements list.
ABTOINTEN : Enables the auto-baud time-out interrupt.
bits : 9 - 18 (10 bit)
Enumeration: test
0 : DISABLE_AUTO_BAUD_TI
Disable auto-baud time-out Interrupt.
1 : ENABLE_AUTO_BAUD_TIM
Enable auto-baud time-out Interrupt.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMMEN : NMM enable.
bits : 0 - 0 (1 bit)
Enumeration: test
0 : DISABLED
RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
1 : ENABLED
RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.
End of enumeration elements list.
RXDIS : Receiver enable.
bits : 1 - 2 (2 bit)
Enumeration: test
0 : THE_RECEIVER_IS_ENAB
The receiver is enabled.
1 : THE_RECEIVER_IS_DISA
The receiver is disabled.
End of enumeration elements list.
AADEN : AAD enable.
bits : 2 - 4 (3 bit)
Enumeration: test
0 : DISABLED
Auto Address Detect (AAD) is disabled.
1 : ENABLED
Auto Address Detect (AAD) is enabled.
End of enumeration elements list.
SEL : Select direction control pin
bits : 3 - 6 (4 bit)
Enumeration: test
0 : RTS
If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.
1 : DTR
If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
End of enumeration elements list.
DCTRL : Auto direction control enable.
bits : 4 - 8 (5 bit)
Enumeration: test
0 : DISABLE_AUTO_DIRECTI
Disable Auto Direction Control.
1 : ENABLE_AUTO_DIRECTIO
Enable Auto Direction Control.
End of enumeration elements list.
OINV : Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
bits : 5 - 10 (6 bit)
Enumeration: test
0 : NORMAL
The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
1 : INVERT
The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
End of enumeration elements list.
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 6 - 37 (32 bit)
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRMATCH : Contains the address match value.
bits : 0 - 7 (8 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RS-485/EIA-485 direction control delay.
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
bits : 0 - 7 (8 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs.
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXFIFILVL : Reflects the current level of the UART receiver FIFO. 0 = empty, 0xF = FIFO full.
bits : 0 - 3 (4 bit)
TXFIFOLVL : Reflects the current level of the UART transmitter FIFO. 0 = empty, 0xF = FIFO full.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
RESERVED : Reserved. The value read from a reserved bit is not defined.
bits : 12 - 43 (32 bit)
Interrupt ID Register. Identifies which interrupt(s) are pending.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSTATUS : Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
bits : 0 - 0 (1 bit)
Enumeration: test
0 : AT_LEAST_ONE_INTERRU
At least one interrupt is pending.
1 : NO_INTERRUPT_IS_PEND
No interrupt is pending.
End of enumeration elements list.
INTID : Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART RX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
bits : 1 - 4 (4 bit)
Enumeration: test
0x3 : RECEIVE_LINE_S
1 - Receive Line Status (RLS).
0x2 : RECEIVE_DATA_AV
2a - Receive Data Available (RDA).
0x6 : CHARACTER_TIME_
2b - Character Time-out Indicator (CTI).
0x1 : THRE_INTERRUPT
3 - THRE Interrupt.
0x0 : MODEM_INTERRUP
4 - Modem interrupt.
End of enumeration elements list.
FIFOENA : These bits are equivalent to FCR[0].
bits : 6 - 13 (8 bit)
ABEOINT : End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
bits : 8 - 16 (9 bit)
ABTOINT : Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
bits : 9 - 18 (10 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
RESERVED : Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
bits : 10 - 41 (32 bit)
FIFO Control Register. Controls UART FIFO usage and modes.
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
alternate_register : IIR
reset_Mask : 0x0
FIFOEN : FIFO Enable
bits : 0 - 0 (1 bit)
Enumeration: test
0 : DISAB
UART FIFOs are disabled. Must not be used in the application.
1 : ENABLE_F
Active high enable for both UART RX and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs.
End of enumeration elements list.
RXFIFORS : RX FIFO Reset
bits : 1 - 2 (2 bit)
Enumeration: test
0 : NO_IMPACT_ON_EITHER_
No impact on either of UART FIFOs.
1 : CLEAR
Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
TXFIFORS : TX FIFO Reset
bits : 2 - 4 (3 bit)
Enumeration: test
0 : NO_IMPACT_ON_EITHER_
No impact on either of UART FIFOs.
1 : CLEAR
Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
DMAMODE : DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 9.5.6.1.
bits : 3 - 6 (4 bit)
Enumeration: test
0 : DMA_NOT_USED_
DMA not used.
1 : DMA_MODE_ENABLED_
DMA mode enabled.
End of enumeration elements list.
RXTL : RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.
bits : 6 - 13 (8 bit)
Enumeration: test
0x0 : TRIGGER_LEVEL_0
Trigger level 0 (1 character or 0x01).
0x1 : TRIGGER_LEVEL_1
Trigger level 1 (4 characters or 0x04).
0x2 : TRIGGER_LEVEL_2
Trigger level 2 (8 characters or 0x08).
0x3 : TRIGGER_LEVEL_3
Trigger level 3 (14 characters or 0x0E).
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
RESERVED : Reserved
bits : 8 - 39 (32 bit)
Line Control Register. Contains controls for frame formatting and break generation.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select
bits : 0 - 1 (2 bit)
Enumeration: test
0x0 : 5_BIT_CHARACTER_LENG
5-bit character length.
0x1 : 6_BIT_CHARACTER_LENG
6-bit character length.
0x2 : 7_BIT_CHARACTER_LENG
7-bit character length.
0x3 : 8_BIT_CHARACTER_LENG
8-bit character length.
End of enumeration elements list.
SBS : Stop Bit Select
bits : 2 - 4 (3 bit)
Enumeration: test
0 : 1_STOP_BIT_
1 stop bit.
1 : 2_STOP_BITS
2 stop bits (1.5 if LCR[1:0]=00).
End of enumeration elements list.
PE : Parity Enable
bits : 3 - 6 (4 bit)
Enumeration: test
0 : DISABLE_PARITY_GENER
Disable parity generation and checking.
1 : ENABLE_PARITY_GENERA
Enable parity generation and checking.
End of enumeration elements list.
PST : Parity Select
bits : 4 - 9 (6 bit)
Enumeration: test
0x0 : ODD_PARITY_NUMBER_O
Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
0x1 : EVEN_PARITY_NUMBER_
Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
0x2 : FORCED_1_STICK_PARIT
Forced 1 stick parity.
0x3 : FORCED_0_STICK_PARIT
Forced 0 stick parity.
End of enumeration elements list.
BC : Break Control
bits : 6 - 12 (7 bit)
Enumeration: test
0 : DISABLE_BREAK_TRANSM
Disable break transmission.
1 : ENABLE_BREAK_TRANSMI
Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high.
End of enumeration elements list.
DLAB : Divisor Latch Access Bit (DLAB)
bits : 7 - 14 (8 bit)
Enumeration: test
0 : DISABLE_ACCESS_TO_DI
Disable access to Divisor Latches.
1 : ENABLE_ACCESS_TO_DIV
Enable access to Divisor Latches.
End of enumeration elements list.
RESERVED : Reserved
bits : 8 - 39 (32 bit)
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