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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

DR0

DR1

DR2

DR3

DR4

DR5

DR6

DR7

STAT

TRM

GDR

INTEN


CR

A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL CLKDIV BURST START EDGE RESERVED RESERVED

SEL : Selects which of the AD7:0 pins is (are) to be sampled and converted. For ADC, bit 0 selects Pin AD0, and bit 7 selects pin AD7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01.
bits : 0 - 7 (8 bit)

CLKDIV : The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 9 MHz. Typically, software should program the smallest value in this field that yields a clock of 9 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
bits : 8 - 23 (16 bit)

BURST : Burst mode control.
bits : 16 - 32 (17 bit)

Enumeration: test

0 : SOFTWARE

Conversions are software controlled and require 36 clocks.

1 : BURST

The AD converter does repeated conversions up to 250 kHz, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start.

End of enumeration elements list.

START : Conversion start control. When the BURST bit is 0, these bits control whether and when an A/D conversion is started.
bits : 24 - 50 (27 bit)

Enumeration: test

0x0 : NOSTART

No start (this value should be used when clearing PDN to 0).

0x1 : START

Start conversion now.

0x2 : STARTONPIO0_2

Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0.

0x3 : STARTONPIO1_5

Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0.

0x4 : STARTONCT32B0_MAT0

Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0.

0x5 : STARTONCT32B0_MAT1

Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1.

0x6 : STARTONCT16B0_MAT0

Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0.

0x7 : STARTONCT16B0_MAT1

Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1.

End of enumeration elements list.

EDGE : Edge control. This bit is significant only when the START field contains 010-111.
bits : 27 - 54 (28 bit)

Enumeration: test

1 : FALLING

Start conversion on a falling edge on the selected CAP/MAT signal.

0 : RISING

Start conversion on a rising edge on the selected CAP/MAT signal.

End of enumeration elements list.

RESERVED : Reserved. These bits always read as zeros.
bits : 28 - 59 (32 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 28 - 59 (32 bit)


DR0

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR0 DR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR1

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR1 DR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR2

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR2 DR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR3

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR3 DR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR4

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR4 DR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR5

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR5 DR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR6

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR6 DR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


DR7

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR7 DR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 45 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.
bits : 31 - 62 (32 bit)


STAT

A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE OVERRUN ADINT RESERVED

DONE : These bits mirror the DONE status flags that appear in the result register for each A/D channel.
bits : 0 - 7 (8 bit)

OVERRUN : These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously.
bits : 8 - 23 (16 bit)

ADINT : This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
bits : 16 - 32 (17 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 17 - 48 (32 bit)


TRM

A/D trim register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRM TRM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCOFFS RESERVED RESERVED

ADCOFFS : Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.
bits : 4 - 11 (8 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 8 - 39 (32 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 8 - 39 (32 bit)


GDR

A/D Global Data Register. Contains the result of the most recent A/D conversion.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDR GDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RESERVED CHN RESERVED RESERVED OVERRUN DONE

RESULT : When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD(3V3) pin: V/VREF. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
bits : 6 - 21 (16 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 16 - 39 (24 bit)

CHN : These bits contain the channel from which the RESULT bits were converted.
bits : 24 - 50 (27 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 27 - 56 (30 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 27 - 56 (30 bit)

OVERRUN : This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.
bits : 30 - 60 (31 bit)

DONE : This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
bits : 31 - 62 (32 bit)


INTEN

A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADINTEN ADGINTEN RESERVED

ADINTEN : These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.
bits : 0 - 7 (8 bit)

ADGINTEN : When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.
bits : 8 - 16 (9 bit)

RESERVED : Reserved. These bits always read as zeros.
bits : 9 - 40 (32 bit)



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