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SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20048 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AHBMATPRIO

PRESETCTRL0

PRESETCTRL1

FXCOMCLKSEL[4]

FXCOMCLKSEL[5]

FXCOMCLKSEL[6]

PIOPORCAP[0]

FXCOMCLKSEL[7]

PIORESCAP[0]

SYSRSTSTAT

AHBCLKCTRL0

BODCTRL

AHBCLKCTRL1

PRESETCTRLSET[0]

PIOPORCAP[1]

PIORESCAP[1]

PRESETCTRLCLR[0]

MAINCLKSELA

MAINCLKSELB

CLKOUTSELA

SYSPLLCLKSEL

ADCCLKSEL

USBCLKSEL

MCLKCLKSEL

FRGCLKSEL

SYSTICKCLKDIV

PRESETCTRLSET[1]

AHBCLKDIV

CLKOUTDIV

ADCCLKDIV

USBCLKDIV

FRGCTRL

MCLKDIV

PRESETCTRLCLR[1]

SYSTCKCAL

FLASHCFG

USBCLKCTRL

USBCLKSTAT

FREQMECTRL

MCLKIO

AHBCLKCTRLSET[0]

NMISRC

AHBCLKCTRLCLR[0]

ASYNCAPBCTRL

FROCTRL

WDTOSCCTRL

RTCOSCCTRL

FXCOMCLKSEL[0]

SYSPLLCTRL

SYSPLLSTAT

SYSPLLNDEC

SYSPLLPDEC

SYSPLLSSCTRL0

SYSPLLSSCTRL1

PDSLEEPCFG0

PDSLEEPCFG1

PDRUNCFG0

PDRUNCFGSET0

PDRUNCFGCLR0

AHBCLKCTRLSET[1]

STARTER0

STARTERSET0

STARTERCLR0

AHBCLKCTRLCLR[1]

HWWAKE

FXCOMCLKSEL[1]

FXCOMCLKSEL[2]

FXCOMCLKSEL[3]

JTAGIDCODE

DEVICE_ID0

DEVICE_ID1


AHBMATPRIO

AHB multilayer matrix priority control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBMATPRIO AHBMATPRIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_ICODE PRI_DCODE PRI_SYS PRI_M0 PRI_USB PRI_DMA

PRI_ICODE : Cortex-M4 I-Code bus priority. Should typically be lower than PRI_DCODE for best operation.
bits : 0 - 1 (2 bit)
access : read-write

PRI_DCODE : Cortex M4 D-Code bus priority.
bits : 2 - 3 (2 bit)
access : read-write

PRI_SYS : Cortex M4 System bus priority.
bits : 4 - 5 (2 bit)
access : read-write

PRI_M0 : Cortex-M0+ bus priority. Present on selected devices.
bits : 6 - 7 (2 bit)
access : read-write

PRI_USB : USB interface priority.
bits : 8 - 9 (2 bit)
access : read-write

PRI_DMA : DMA controller priority.
bits : 10 - 11 (2 bit)
access : read-write


PRESETCTRL0

Peripheral reset control n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRL0 PRESETCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_RST FMC_RST MUX_RST IOCON_RST GPIO0_RST GPIO1_RST PINT_RST GINT_RST DMA0_RST CRC_RST WWDT_RST ADC0_RST

FLASH_RST : Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 7 - 7 (1 bit)
access : read-write

FMC_RST : Flash accelerator reset control. Note that the FMC must not be reset while executing from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 8 - 8 (1 bit)
access : read-write

MUX_RST : Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 11 - 11 (1 bit)
access : read-write

IOCON_RST : IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write

GPIO0_RST : GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write

GPIO1_RST : GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 15 - 15 (1 bit)
access : read-write

PINT_RST : Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 18 - 18 (1 bit)
access : read-write

GINT_RST : Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 19 - 19 (1 bit)
access : read-write

DMA0_RST : DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 20 - 20 (1 bit)
access : read-write

CRC_RST : CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 21 - 21 (1 bit)
access : read-write

WWDT_RST : Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 22 - 22 (1 bit)
access : read-write

ADC0_RST : ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 27 - 27 (1 bit)
access : read-write


PRESETCTRL1

Peripheral reset control n
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRL1 PRESETCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRT0_RST SCT0_RST UTICK0_RST FC0_RST FC1_RST FC2_RST FC3_RST FC4_RST FC5_RST FC6_RST FC7_RST USB0_RST CTIMER0_RST CTIMER1_RST

MRT0_RST : Multi-rate timer (MRT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 0 - 0 (1 bit)
access : read-write

SCT0_RST : State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 2 - 2 (1 bit)
access : read-write

UTICK0_RST : Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 10 - 10 (1 bit)
access : read-write

FC0_RST : Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 11 - 11 (1 bit)
access : read-write

FC1_RST : Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 12 - 12 (1 bit)
access : read-write

FC2_RST : Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write

FC3_RST : Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write

FC4_RST : Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 15 - 15 (1 bit)
access : read-write

FC5_RST : Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 16 - 16 (1 bit)
access : read-write

FC6_RST : Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 17 - 17 (1 bit)
access : read-write

FC7_RST : Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 18 - 18 (1 bit)
access : read-write

USB0_RST : USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 25 - 25 (1 bit)
access : read-write

CTIMER0_RST : CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 26 - 26 (1 bit)
access : read-write

CTIMER1_RST : CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 27 - 27 (1 bit)
access : read-write


FXCOMCLKSEL[4]

Flexcomm0 clock source select
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[4] FXCOMCLKSEL[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


FXCOMCLKSEL[5]

Flexcomm0 clock source select
address_offset : 0x130C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[5] FXCOMCLKSEL[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


FXCOMCLKSEL[6]

Flexcomm0 clock source select
address_offset : 0x15D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[6] FXCOMCLKSEL[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


PIOPORCAP[0]

POR captured value of port n
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIOPORCAP[0] PIOPORCAP[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOPORCAP

PIOPORCAP : State of PIOn_31 through PIOn_0 at power-on reset
bits : 0 - 31 (32 bit)
access : read-only


FXCOMCLKSEL[7]

Flexcomm0 clock source select
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[7] FXCOMCLKSEL[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


PIORESCAP[0]

Reset captured value of port n
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIORESCAP[0] PIORESCAP[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIORESCAP

PIORESCAP : State of PIOn_31 through PIOn_0 for resets other than POR.
bits : 0 - 31 (32 bit)
access : read-only


SYSRSTSTAT

System reset status register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSRSTSTAT SYSRSTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR EXTRST WDT BOD SYSRST

POR : POR reset status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NO_POR_DETECTED

No POR detected

0x1 : POR_DETECTED

POR detected. Writing a one clears this reset.

End of enumeration elements list.

EXTRST : Status of the external RESET pin. External reset status
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NO_RESET_DETECTED

No reset event detected.

0x1 : RESET_DETECTED

Reset detected. Writing a one clears this reset.

End of enumeration elements list.

WDT : Status of the Watchdog reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NO_WDT_RESET_DETECTED

No WDT reset detected

0x1 : WDT_RESET_DETECTED

WDT reset detected. Writing a one clears this reset.

End of enumeration elements list.

BOD : Status of the Brown-out detect reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NO_BOD_RESET_DETECTED

No BOD reset detected

0x1 : BOD_RESET_DETECTED

BOD reset detected. Writing a one clears this reset.

End of enumeration elements list.

SYSRST : Status of the software system reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NO_SYSTEM_RESET_DETECTED

No System reset detected

0x1 : SYSTEM_RESET_DETECTED

System reset detected. Writing a one clears this reset.

End of enumeration elements list.


AHBCLKCTRL0

AHB Clock control n
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRL0 AHBCLKCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM FLASH FMC INPUTMUX IOCON GPIO0 GPIO1 PINT GINT DMA0 CRC WWDT RTC ADC0

ROM : Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
bits : 1 - 1 (1 bit)
access : read-write

FLASH : Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming, not for flash read.
bits : 7 - 7 (1 bit)
access : read-write

FMC : Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read.
bits : 8 - 8 (1 bit)
access : read-write

INPUTMUX : Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
bits : 11 - 11 (1 bit)
access : read-write

IOCON : Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write

GPIO0 : Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write

GPIO1 : Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
bits : 15 - 15 (1 bit)
access : read-write

PINT : Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
bits : 18 - 18 (1 bit)
access : read-write

GINT : Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
bits : 19 - 19 (1 bit)
access : read-write

DMA0 : Enables the clock for the DMA0 controller. 0 = Disable; 1 = Enable.
bits : 20 - 20 (1 bit)
access : read-write

CRC : Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
bits : 21 - 21 (1 bit)
access : read-write

WWDT : Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
bits : 22 - 22 (1 bit)
access : read-write

RTC : Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.
bits : 23 - 23 (1 bit)
access : read-write

ADC0 : Enables the clock for the ADC0 register interface. 0 = Disable; 1 = Enable.
bits : 27 - 27 (1 bit)
access : read-write


BODCTRL

Brown-Out Detect control
address_offset : 0x20044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODCTRL BODCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODRSTLEV BODRSTENA BODINTLEV BODINTENA BODRSTSTAT BODINTSTAT

BODRSTLEV : BOD reset level
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : LEVEL0

Level 0: 1.5 V

0x1 : LEVEL1

Level 1: 1.85 V

0x2 : LEVEL2

Level 2: 2.0 V

0x3 : LEVEL3

Level 3: 2.3 V

End of enumeration elements list.

BODRSTENA : BOD reset enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable reset function.

0x1 : ENABLE

Enable reset function.

End of enumeration elements list.

BODINTLEV : BOD interrupt level
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : LEVEL0

Level 0: 2.05 V

0x1 : LEVEL1

Level 1: 2.45 V

0x2 : LEVEL2

Level 2: 2.75 V

0x3 : LEVEL3

Level 3: 3.05 V

End of enumeration elements list.

BODINTENA : BOD interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable interrupt function.

0x1 : ENABLE

Enable interrupt function.

End of enumeration elements list.

BODRSTSTAT : BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write

BODINTSTAT : BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.
bits : 7 - 7 (1 bit)
access : read-write


AHBCLKCTRL1

AHB Clock control n
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRL1 AHBCLKCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MRT0 SCT0 UTICK0 FLEXCOMM0 FLEXCOMM1 FLEXCOMM2 FLEXCOMM3 FLEXCOMM4 FLEXCOMM5 FLEXCOMM6 FLEXCOMM7 USB0 CTIMER0 CTIMER1

MRT0 : Enables the clock for the Multi-Rate Timer. 0 = Disable; 1 = Enable.
bits : 0 - 0 (1 bit)
access : read-write

SCT0 : Enables the clock for SCT0. 0 = Disable; 1 = Enable.
bits : 2 - 2 (1 bit)
access : read-write

UTICK0 : Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
bits : 10 - 10 (1 bit)
access : read-write

FLEXCOMM0 : Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.
bits : 11 - 11 (1 bit)
access : read-write

FLEXCOMM1 : Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.
bits : 12 - 12 (1 bit)
access : read-write

FLEXCOMM2 : Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write

FLEXCOMM3 : Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write

FLEXCOMM4 : Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.
bits : 15 - 15 (1 bit)
access : read-write

FLEXCOMM5 : Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.
bits : 16 - 16 (1 bit)
access : read-write

FLEXCOMM6 : Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.
bits : 17 - 17 (1 bit)
access : read-write

FLEXCOMM7 : Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.
bits : 18 - 18 (1 bit)
access : read-write

USB0 : Enables the clock for the USB0 interface. 0 = Disable; 1 = Enable.
bits : 25 - 25 (1 bit)
access : read-write

CTIMER0 : Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.
bits : 26 - 26 (1 bit)
access : read-write

CTIMER1 : Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.
bits : 27 - 27 (1 bit)
access : read-write


PRESETCTRLSET[0]

Set bits in PRESETCTRLn
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRLSET[0] PRESETCTRLSET[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST_SET

RST_SET : Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


PIOPORCAP[1]

POR captured value of port n
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIOPORCAP[1] PIOPORCAP[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOPORCAP

PIOPORCAP : State of PIOn_31 through PIOn_0 at power-on reset
bits : 0 - 31 (32 bit)
access : read-only


PIORESCAP[1]

Reset captured value of port n
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIORESCAP[1] PIORESCAP[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIORESCAP

PIORESCAP : State of PIOn_31 through PIOn_0 for resets other than POR.
bits : 0 - 31 (32 bit)
access : read-only


PRESETCTRLCLR[0]

Clear bits in PRESETCTRLn
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRLCLR[0] PRESETCTRLCLR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST_CLR

RST_CLR : Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


MAINCLKSELA

Main clock source select A
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAINCLKSELA MAINCLKSELA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Clock source for main clock source selector A
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : CLKIN

CLKIN (clk_in)

0x2 : WATCHDOG_OSCILLATOR

Watchdog oscillator (wdt_clk)

0x3 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

End of enumeration elements list.


MAINCLKSELB

Main clock source select B
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAINCLKSELB MAINCLKSELB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Clock source for main clock source selector B. Selects the clock source for the main clock.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : MAINCLKSELA

MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : RTC_OSC_OUTPUT

RTC oscillator 32 kHz output (32k_clk)

End of enumeration elements list.


CLKOUTSELA

CLKOUT clock source select A
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTSELA CLKOUTSELA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : CLKOUT clock source selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : MAIN_CLOCK

Main clock (main_clk)

0x1 : CLKIN

CLKIN (clk_in)

0x2 : WATCHDOG_OSCILLATOR

Watchdog oscillator (wdt_clk)

0x3 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x4 : SYSTEM_PLL_OUTPUT

PLL output (pll_clk)

0x5 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x6 : RTC_OSC_OUTPUT

RTC oscillator 32 kHz output (32k_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


SYSPLLCLKSEL

PLL clock source select
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLCLKSEL SYSPLLCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : System PLL clock source selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : CLKIN

CLKIN (clk_in)

0x3 : RTC_32_KHZ_CLOCK

RTC 32 kHz clock (32k_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


ADCCLKSEL

ADC clock source select
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCCLKSEL ADCCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : ADC clock source selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : MAIN_CLOCK

Main clock (main_clk)

0x1 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x2 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


USBCLKSEL

USB clock source select
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCLKSEL USBCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : USB device clock source selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x1 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x2 : MAIN_CLOCK

Main clock (main_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


MCLKCLKSEL

MCLK clock source select
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLKCLKSEL MCLKCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x1 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x2 : MAIN_CLOCK

Main clock (main_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


FRGCLKSEL

Fractional Rate Generator clock source select
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRGCLKSEL FRGCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Fractional Rate Generator clock source select.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : MAIN_CLOCK

Main clock (main_clk)

0x1 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x2 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x3 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


SYSTICKCLKDIV

SYSTICK clock divider
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTICKCLKDIV SYSTICKCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


PRESETCTRLSET[1]

Set bits in PRESETCTRLn
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRLSET[1] PRESETCTRLSET[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST_SET

RST_SET : Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


AHBCLKDIV

AHB clock divider
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLKDIV AHBCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


CLKOUTDIV

CLKOUT clock divider
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTDIV CLKOUTDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


ADCCLKDIV

ADC clock divider
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCCLKDIV ADCCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


USBCLKDIV

USB clock divider
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCLKDIV USBCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


FRGCTRL

Fractional rate divider
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRGCTRL FRGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV MULT

DIV : Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
bits : 0 - 7 (8 bit)
access : read-write

MULT : Numerator of the fractional divider. MULT is equal to the programmed value.
bits : 8 - 15 (8 bit)
access : read-write


MCLKDIV

I2S MCLK clock divider
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLKDIV MCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write


PRESETCTRLCLR[1]

Clear bits in PRESETCTRLn
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRLCLR[1] PRESETCTRLCLR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST_CLR

RST_CLR : Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


SYSTCKCAL

System tick counter calibration
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTCKCAL SYSTCKCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL SKEW NOREF

CAL : System tick timer calibration value.
bits : 0 - 23 (24 bit)
access : read-write

SKEW : Initial value for the Systick timer.
bits : 24 - 24 (1 bit)
access : read-write

NOREF : Initial value for the Systick timer.
bits : 25 - 25 (1 bit)
access : read-write


FLASHCFG

Flash wait states configuration
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLASHCFG FLASHCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FETCHCFG DATACFG ACCEL PREFEN PREFOVR FLASHTIM

FETCHCFG : Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : NO_BUFFER

Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled.

0x1 : ONE_BUFFER

One buffer is used for all instruction fetches.

0x2 : ALL_BUFFERS

All buffers may be used for instruction fetches.

End of enumeration elements list.

DATACFG : Data read configuration. This field determines how flash accelerator buffers are used for data accesses.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : NOT_BUFFERED

Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory.

0x1 : ONE_BUFFER

One buffer is used for all data accesses.

0x2 : ALL_BUFFERS

All buffers may be used for data accesses.

End of enumeration elements list.

ACCEL : Acceleration enable.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance.

0x1 : ENABLED

Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings.

End of enumeration elements list.

PREFEN : Prefetch enable.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NO_PREFETCH

No instruction prefetch is performed.

0x1 : PREFETCH

If the FETCHCFG field is not 0, the next flash line following the current execution address is automatically prefetched if it is not already buffered.

End of enumeration elements list.

PREFOVR : Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : PREFETCH_COMPLETED

Any previously initiated prefetch will be completed.

0x1 : PREFETCH_ABORT

Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered.

End of enumeration elements list.

FLASHTIM : Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1.
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

0 : N_1_CLOCK_CYCLE

1 system clock flash access time (for system clock rates up to 12 MHz).

0x1 : N_2_CLOCK_CYCLES

2 system clocks flash access time (for system clock rates up to 30 MHz).

0x2 : N_3_CLOCK_CYCLES

3 system clocks flash access time (for system clock rates up to 60 MHz).

0x3 : N_4_CLOCK_CYCLES

4 system clocks flash access time (for system clock rates up to 85 MHz).

0x4 : N_5_CLOCK_CYCLES

5 system clocks flash access time (for system clock rates up to 100 MHz).

End of enumeration elements list.


USBCLKCTRL

USB clock control
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCLKCTRL USBCLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POL_CLK

POL_CLK : USB_NEED_CLK polarity for triggering the USB wake-up interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : FALLING_EDGE

Falling edge of the USB_NEED_CLK triggers the USB wake-up (default).

0x1 : RISING_EDGE

Rising edge of the USB_NEED_CLK triggers the USB wake-up.

End of enumeration elements list.


USBCLKSTAT

USB clock status
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCLKSTAT USBCLKSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEED_CLKST

NEED_CLKST : USB_NEED_CLK signal status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : LOW

Low

0x1 : HIGH

High

End of enumeration elements list.


FREQMECTRL

Frequency measure register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQMECTRL FREQMECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPVAL PROG

CAPVAL : Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
bits : 0 - 13 (14 bit)
access : read-write

PROG : Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0).
bits : 31 - 31 (1 bit)
access : read-write


MCLKIO

MCLK input/output control
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLKIO MCLKIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR

DIR : MCLK direction control.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : INPUT

The MCLK function is an input.

0x1 : OUTPUT

The MCLK function is an output.

End of enumeration elements list.


AHBCLKCTRLSET[0]

Set bits in AHBCLKCTRLn
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRLSET[0] AHBCLKCTRLSET[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SET

CLK_SET : Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


NMISRC

NMI Source Select
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMISRC NMISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQM4 IRQM0 NMIENM0 NMIENM4

IRQM4 : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
bits : 0 - 5 (6 bit)
access : read-write

IRQM0 : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M0+, if enabled by NMIENM0. Present on selected devices.
bits : 8 - 13 (6 bit)
access : read-write

NMIENM0 : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM0. Present on selected devices.
bits : 30 - 30 (1 bit)
access : read-write

NMIENM4 : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
bits : 31 - 31 (1 bit)
access : read-write


AHBCLKCTRLCLR[0]

Clear bits in AHBCLKCTRLn
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRLCLR[0] AHBCLKCTRLCLR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_CLR

CLK_CLR : Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


ASYNCAPBCTRL

Asynchronous APB Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNCAPBCTRL ASYNCAPBCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE

ENABLE : Enables the asynchronous APB bridge and subsystem.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. Asynchronous APB bridge is disabled.

0x1 : ENABLED

Enabled. Asynchronous APB bridge is enabled.

End of enumeration elements list.


FROCTRL

FRO oscillator control
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FROCTRL FROCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM SEL FREQTRIM USBCLKADJ USBMODCHG HSPDCLK WRTRIM

TRIM : This value is factory trimmed to account for bias and temperature compensation. The value should not be changed by software. Also see the WRTRIM bit description.
bits : 0 - 13 (14 bit)
access : read-write

SEL : Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : FRQ_48_MHZ

48 MHz

0x1 : FRQ_96_MHZ

96 MHz

End of enumeration elements list.

FREQTRIM : Frequency trim. Boot code configures this to a device-specific factory trim value for the 48 MHz FRO. If USBCLKADJ = 1, this field is read-only and provides the value resulting from USB rate adjustment. See the USBMODCFG flag regarding reading this field. Application code may adjust this field when USBCLKADJ = 0. A single step of FREQTRIM is roughly equivalent to 0.1% of the selected FRO frequency.
bits : 16 - 23 (8 bit)
access : read-write

USBCLKADJ : USB clock adjust mode.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

Normal operation.

0x1 : AUTO_USB_ADJUST

Automatic USB rate adjustment mode. If the USB FS device peripheral is enabled and connected to a USB host, it provides clock adjustment information to the FRO based on SOF packets. USB rate adjustment requires a number of cycles to take place. the USBMODCHG bit (see below) indicates when initial adjustment is complete, and when later adjustments are in progress. software must not alter TRIM and FREQTRIM while USBCLKADJ = 1. see USBCLKADJ usage notes below this table.

End of enumeration elements list.

USBMODCHG : USB Mode value Change flag. When 1, indicates that the USB trim is currently being updated (or is still starting up) and software should wait to read FREQTRIM. Update occurs at most once per millisecond.
bits : 25 - 25 (1 bit)
access : read-write

HSPDCLK : High speed clock enable. Allows disabling the highs-speed FRO output if it is not needed.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

The high-speed FRO output is disabled.

0x1 : ENABLED

The selected high-speed FRO output (48 MHz or 96 MHz) is enabled.

End of enumeration elements list.

WRTRIM : Write Trim value. Must be written to 1 to modify the SEL or TRIM fields, during the same write. This bit always reads as 0.
bits : 31 - 31 (1 bit)
access : read-write


WDTOSCCTRL

Watchdog oscillator control
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTOSCCTRL WDTOSCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSEL FREQSEL

DIVSEL : Divider select. Selects the value of the divider that adjusts the output of the oscillator. 0x00 = divide by 2 0x01 = divide by 4 0x02 = divide by 6 up to 0x1E = divide by 62 0x1F = divide by 64
bits : 0 - 4 (5 bit)
access : read-write

FREQSEL : Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x01 = 0.4 MHz 0x02 = 0.6 MHz 0x03 = 0.75 MHz 0x04 = 0.9 MHz 0x05 = 1.0 MHz 0x06 = 1.2 MHz 0x07 = 1.3 MHz 0x08 = 1.4 MHz 0x09 = 1.5 MHz 0x0A = 1.6 MHz 0x0B = 1.7 MHz 0x0C = 1.8 MHz 0x0D = 1.9 MHz 0x0E = 2.0 MHz 0x0F = 2.05 MHz 0x10 = 2.1 MHz 0x11 = 2.2 MHz 0x12 = 2.25 MHz 0x13 = 2.3 MHz 0x14 = 2.4 MHz 0x15 = 2.45 MHz 0x16 = 2.5 MHz 0x17 = 2.6 MHz 0x18 = 2.65 MHz 0x19 = 2.7 MHz 0x1A = 2.8 MHz 0x1B = 2.85 MHz 0x1C = 2.9 MHz 0x1D = 2.95 MHz 0x1E = 3.0 MHz 0x1F = 3.05 MHz
bits : 5 - 9 (5 bit)
access : read-write


RTCOSCCTRL

RTC oscillator 32 kHz output control
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCOSCCTRL RTCOSCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : RTC 32 kHz clock enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. RTC clock off.

0x1 : ENABLED

Enabled. RTC clock on.

End of enumeration elements list.


FXCOMCLKSEL[0]

Flexcomm0 clock source select
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[0] FXCOMCLKSEL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


SYSPLLCTRL

PLL control
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLCTRL SYSPLLCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELR SELI SELP BYPASS BYPASSCCODIV2 UPLIMOFF BANDSEL DIRECTI DIRECTO

SELR : Bandwidth select R value
bits : 0 - 3 (4 bit)
access : read-write

SELI : Bandwidth select I value.
bits : 4 - 9 (6 bit)
access : read-write

SELP : Bandwidth select P value
bits : 10 - 14 (5 bit)
access : read-write

BYPASS : PLL bypass control.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Bypass disabled. PLL CCO is sent to the PLL post-dividers.

0x1 : ENABLED

Bypass enabled. PLL input clock is sent directly to the PLL output (default).

End of enumeration elements list.

BYPASSCCODIV2 : Bypass feedback clock divide by 2.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DIVIDE_BY_2

Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide.

0x1 : BYPASS

Bypass. The CCO feedback clock is divided only by the programmed M divide.

End of enumeration elements list.

UPLIMOFF : Disable upper frequency limiter.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

Normal mode.

0x1 : DISABLED

Upper frequency limiter disabled.

End of enumeration elements list.

BANDSEL : PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SSCG_CONTROL

SSCG control. The PLL filter uses the parameters derived from the spread spectrum controller.

0x1 : MDEC_CONTROL

MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants.

End of enumeration elements list.

DIRECTI : PLL0 direct input enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO.

0x1 : ENABLED

Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input.

End of enumeration elements list.

DIRECTO : PLL0 direct output enable.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. The PLL output divider (P divider) is used to create the PLL output.

0x1 : ENABLED

Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.

End of enumeration elements list.


SYSPLLSTAT

PLL status
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSPLLSTAT SYSPLLSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : PLL0 lock indicator
bits : 0 - 0 (1 bit)
access : read-only


SYSPLLNDEC

PLL N decoder
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLNDEC SYSPLLNDEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDEC NREQ

NDEC : Decoded N-divider coefficient value.
bits : 0 - 9 (10 bit)
access : read-write

NREQ : NDEC reload request. When a 1 is written to this bit, the NDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the NDEC value is changed.
bits : 10 - 10 (1 bit)
access : read-write


SYSPLLPDEC

PLL P decoder
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLPDEC SYSPLLPDEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDEC PREQ

PDEC : Decoded P-divider coefficient value.
bits : 0 - 6 (7 bit)
access : read-write

PREQ : PDEC reload request. When a 1 is written to this bit, the PDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the PDEC value is changed.
bits : 7 - 7 (1 bit)
access : read-write


SYSPLLSSCTRL0

PLL spread spectrum control 0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLSSCTRL0 SYSPLLSSCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDEC MREQ SEL_EXT

MDEC : Decoded M-divider coefficient value.
bits : 0 - 16 (17 bit)
access : read-write

MREQ : MDEC reload request. When a 1 is written to this bit, the MDEC value is loaded into the PLL. Must be cleared by software for any subsequent load, or the PLL can be powered down and back up via the PDEN_SYS_PLL bit in the PDRUNCFG register if the MDEC value is changed.
bits : 17 - 17 (1 bit)
access : read-write

SEL_EXT : Select spread spectrum mode. Selects the source of the feedback divider value. For normal mode, this must be the value from the MDEC field in this register. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1.
bits : 18 - 18 (1 bit)
access : read-write


SYSPLLSSCTRL1

PLL spread spectrum control 1
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLSSCTRL1 SYSPLLSSCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD MDREQ MF MR MC PD DITHER

MD : M- divider value with fraction. MD[18:11]: integer portion of the feedback divider value. MD[10:0]: fractional portion of the feedback divider value. In fractional mode, fcco = (2 - BYPASSCCODIV2) x (MD x 2^-11) x Fref
bits : 0 - 18 (19 bit)
access : read-write

MDREQ : MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete
bits : 19 - 19 (1 bit)
access : read-write

MF : Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm _ 3.9 - 7.8 kHz) 0b001 => Nss _ 384 (fm _ 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm _ 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm _ 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm _ 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm _ 62.5- 125 kHz) 0b110 => Nss _ 24 (fm _ 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm _ 125- 250 kHz)
bits : 20 - 22 (3 bit)
access : read-write

MR : Programmable frequency modulation depth. 0 = no spread. _fmodpk-pk = Fref x k/Fcco = k/MDdec 0b000 -> k = 0 (no spread spectrum) 0b001 => k _ 1 0b010 => k _ 1.5 0b011 => k _ 2 0b100 => k _ 3 0b101 => k _ 4 0b110 => k _ 6 0b111 => k _ 8
bits : 23 - 25 (3 bit)
access : read-write

MC : Modulation waveform control. 0 = no compensation. Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation
bits : 26 - 27 (2 bit)
access : read-write

PD : Spread spectrum power-down.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : ENABLED

Enabled. Spread spectrum controller is enabled

0x1 : DISABLED

Disabled. Spread spectrum controller is disabled.

End of enumeration elements list.

DITHER : Select modulation frequency.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : FIXED

Fixed. Fixed modulation frequency.

0x1 : DITHER

Dither. Randomly dither between two modulation frequencies.

End of enumeration elements list.


PDSLEEPCFG0

Sleep configuration register n
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSLEEPCFG0 PDSLEEPCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD_SLEEP

PD_SLEEP : See bit descriptions in the PDRUNCFGn register.
bits : 0 - 31 (32 bit)
access : read-write


PDSLEEPCFG1

Sleep configuration register n
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSLEEPCFG1 PDSLEEPCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD_SLEEP

PD_SLEEP : See bit descriptions in the PDRUNCFGn register.
bits : 0 - 31 (32 bit)
access : read-write


PDRUNCFG0

Power configuration register 0
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDRUNCFG0 PDRUNCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDEN_FRO PDEN_TS PDEN_BOD_RST PDEN_BOD_INTR PDEN_ADC0 PDEN_SRAM0 PDEN_SRAMX PDEN_ROM PDEN_VDDA PDEN_WDT_OSC PDEN_USB_PHY PDEN_SYS_PLL PDEN_VREFP

PDEN_FRO : FRO oscillator. 0 = Powered; 1 = Powered down.
bits : 4 - 4 (1 bit)
access : read-write

PDEN_TS : Temp sensor. 0 = Powered; 1 = Powered down.
bits : 6 - 6 (1 bit)
access : read-write

PDEN_BOD_RST : Brown-out Detect reset. 0 = Powered; 1 = Powered down.
bits : 7 - 7 (1 bit)
access : read-write

PDEN_BOD_INTR : Brown-out Detect interrupt. 0 = Powered; 1 = Powered down.
bits : 8 - 8 (1 bit)
access : read-write

PDEN_ADC0 : ADC0. 0 = Powered; 1 = Powered down.
bits : 10 - 10 (1 bit)
access : read-write

PDEN_SRAM0 : SRAM0. 0 = Powered; 1 = Powered down.
bits : 13 - 13 (1 bit)
access : read-write

PDEN_SRAMX : SRAMX. 0 = Powered; 1 = Powered down.
bits : 16 - 16 (1 bit)
access : read-write

PDEN_ROM : ROM. 0 = Powered; 1 = Powered down.
bits : 17 - 17 (1 bit)
access : read-write

PDEN_VDDA : Vdda to the ADC, must be enabled for the ADC to work. Also see bit 23. 0 = Powered; 1 = Powered down.
bits : 19 - 19 (1 bit)
access : read-write

PDEN_WDT_OSC : Watchdog oscillator. 0 = Powered; 1 = Powered down.
bits : 20 - 20 (1 bit)
access : read-write

PDEN_USB_PHY : USB pin interface. 0 = Powered; 1 = Powered down.
bits : 21 - 21 (1 bit)
access : read-write

PDEN_SYS_PLL : PLL0. 0 = Powered; 1 = Powered down.
bits : 22 - 22 (1 bit)
access : read-write

PDEN_VREFP : Vrefp to the ADC, must be enabled for the ADC to work. Also see bit 19. 0 = Powered; 1 = Powered down.
bits : 23 - 23 (1 bit)
access : read-write


PDRUNCFGSET0

Set bits in PDRUNCFGn
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDRUNCFGSET0 PDRUNCFGSET0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD_SET

PD_SET : Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


PDRUNCFGCLR0

Clear bits in PDRUNCFGn
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDRUNCFGCLR0 PDRUNCFGCLR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD_CLR

PD_CLR : Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG register, if they are implemented. Bits that do not correspond to defined bits in PDRUNCFG are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


AHBCLKCTRLSET[1]

Set bits in AHBCLKCTRLn
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRLSET[1] AHBCLKCTRLSET[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SET

CLK_SET : Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


STARTER0

Start logic n wake-up enable register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTER0 STARTER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_BOD DMA0 GINT0 GINT1 PIN_INT0 PIN_INT1 PIN_INT2 PIN_INT3 UTICK0 MRT0 CTIMER0 CTIMER1 SCT0 CTIMER3 FLEXCOMM0 FLEXCOMM1 FLEXCOMM2 FLEXCOMM3 FLEXCOMM4 FLEXCOMM5 FLEXCOMM6 FLEXCOMM7 USB0_NEEDCLK USB0 RTC

WDT_BOD : WWDT and BOD interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 0 - 0 (1 bit)
access : read-write

DMA0 : DMA0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 1 - 1 (1 bit)
access : read-write

GINT0 : Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 2 - 2 (1 bit)
access : read-write

GINT1 : Group interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 3 - 3 (1 bit)
access : read-write

PIN_INT0 : GPIO pin interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
bits : 4 - 4 (1 bit)
access : read-write

PIN_INT1 : GPIO pin interrupt 1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
bits : 5 - 5 (1 bit)
access : read-write

PIN_INT2 : GPIO pin interrupt 2 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
bits : 6 - 6 (1 bit)
access : read-write

PIN_INT3 : GPIO pin interrupt 3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
bits : 7 - 7 (1 bit)
access : read-write

UTICK0 : Micro-tick Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 8 - 8 (1 bit)
access : read-write

MRT0 : Multi-Rate Timer wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 9 - 9 (1 bit)
access : read-write

CTIMER0 : Standard counter/timer CTIMER0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 10 - 10 (1 bit)
access : read-write

CTIMER1 : Standard counter/timer CTIMER1 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 11 - 11 (1 bit)
access : read-write

SCT0 : SCT0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 12 - 12 (1 bit)
access : read-write

CTIMER3 : Standard counter/timer CTIMER3 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.
bits : 13 - 13 (1 bit)
access : read-write

FLEXCOMM0 : Flexcomm0 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 14 - 14 (1 bit)
access : read-write

FLEXCOMM1 : Flexcomm1 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 15 - 15 (1 bit)
access : read-write

FLEXCOMM2 : Flexcomm2 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 16 - 16 (1 bit)
access : read-write

FLEXCOMM3 : Flexcomm3 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 17 - 17 (1 bit)
access : read-write

FLEXCOMM4 : Flexcomm4 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 18 - 18 (1 bit)
access : read-write

FLEXCOMM5 : Flexcomm5 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 19 - 19 (1 bit)
access : read-write

FLEXCOMM6 : Flexcomm6 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 20 - 20 (1 bit)
access : read-write

FLEXCOMM7 : Flexcomm7 peripheral interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 21 - 21 (1 bit)
access : read-write

USB0_NEEDCLK : USB0 activity interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 27 - 27 (1 bit)
access : read-write

USB0 : USB0 function interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 28 - 28 (1 bit)
access : read-write

RTC : RTC interrupt alarm and wake-up timer. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 29 - 29 (1 bit)
access : read-write


STARTERSET0

Set bits in STARTERn
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STARTERSET0 STARTERSET0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_SET

START_SET : Writing ones to this register sets the corresponding bit or bits in the STARTERn register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


STARTERCLR0

Clear bits in STARTERn
address_offset : 0x6C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

STARTERCLR0 STARTERCLR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CLR

START_CLR : Writing ones to this register clears the corresponding bit or bits in the STARTERn register, if they are implemented. Bits that do not correspond to defined bits in STARTERn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


AHBCLKCTRLCLR[1]

Clear bits in AHBCLKCTRLn
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AHBCLKCTRLCLR[1] AHBCLKCTRLCLR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_CLR

CLK_CLR : Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


HWWAKE

Configures special cases of hardware wake-up
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HWWAKE HWWAKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCEWAKE FCWAKE WAKEDMA

FORCEWAKE : Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to continue operating while the main CPU(s) are shut down.
bits : 0 - 0 (1 bit)
access : read-write

FCWAKE : Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted.
bits : 1 - 1 (1 bit)
access : read-write

WAKEDMA : Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity.
bits : 3 - 3 (1 bit)
access : read-write


FXCOMCLKSEL[1]

Flexcomm0 clock source select
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[1] FXCOMCLKSEL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


FXCOMCLKSEL[2]

Flexcomm0 clock source select
address_offset : 0xACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[2] FXCOMCLKSEL[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


FXCOMCLKSEL[3]

Flexcomm0 clock source select
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FXCOMCLKSEL[3] FXCOMCLKSEL[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x1 : FRO_HF

FRO 96 or 48 MHz (fro_hf)

0x2 : SYSTEM_PLL_OUTPUT

System PLL output (pll_clk)

0x3 : MCLK_INPUT

MCLK pin input, when selected in IOCON (mclk_in)

0x4 : FRG_CLOCK_OUTPUT

FRG clock, the output of the fractional rate generator (frg_clk)

0x7 : NONE

None, this may be selected in order to reduce power when no output is needed.

End of enumeration elements list.


JTAGIDCODE

JTAG ID code register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

JTAGIDCODE JTAGIDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JTAGID

JTAGID : JTAG ID code.
bits : 0 - 31 (32 bit)
access : read-only


DEVICE_ID0

Part ID register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ID0 DEVICE_ID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTID

PARTID : Part ID
bits : 0 - 31 (32 bit)
access : read-only


DEVICE_ID1

Boot ROM and die revision register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ID1 DEVICE_ID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVID

REVID : Revision.
bits : 0 - 31 (32 bit)
access : read-only



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