Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
SPIFI control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again.
bits : 0 - 15 (16 bit)
access : read-write
CSHIGH : This field controls the minimum CS high time, expressed as a number of serial clock periods minus one.
bits : 16 - 19 (4 bit)
access : read-write
D_PRFTCH_DIS : This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses.
bits : 21 - 21 (1 bit)
access : read-write
INTEN : If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details.
bits : 22 - 22 (1 bit)
access : read-write
MODE3 : SPI Mode 3 select.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SCK_LOW
SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH.
0x1 : SCK_HIGH
SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.) MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
End of enumeration elements list.
PRFTCH_DIS : Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : ENABLE
Enable. Cache prefetching enabled.
0x1 : DISABLE
Disable. Disables prefetching of cache lines.
End of enumeration elements list.
DUAL : Select dual protocol.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : QUAD
Quad protocol. This protocol uses IO3:0.
0x1 : DUAL
Dual protocol. This protocol uses IO1:0.
End of enumeration elements list.
RFCLK : Select active clock edge for input data.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : RISING_EDGE
Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation.
0x1 : FALLING_EDGE
Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
End of enumeration elements list.
FBCLK : Feedback clock select.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : INTERNAL_CLOCK
Internal clock. The SPIFI samples read data using an internal clock.
0x1 : FEEDBACK_CLOCK
Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
End of enumeration elements list.
DMAEN : A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DMAEN should only be used in Command mode.
bits : 31 - 31 (1 bit)
access : read-write
SPIFI limit register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLIMIT : Zero-based upper limit of cacheable memory
bits : 0 - 31 (32 bit)
access : read-write
SPIFI data register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Input or output data
bits : 0 - 31 (32 bit)
access : read-write
SPIFI memory command register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLL : This bit should be written as 0.
bits : 14 - 14 (1 bit)
access : read-write
DOUT : This bit should be written as 0.
bits : 15 - 15 (1 bit)
access : read-write
INTLEN : This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.
bits : 16 - 18 (3 bit)
access : read-write
FIELDFORM : This field controls how the fields of the command are sent.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : ALL_SERIAL
All serial. All fields of the command are serial.
0x1 : QUAD_DUAL_DATA
Quad/dual data. Data field is quad/dual, other fields are serial.
0x2 : SERIAL_OPCODE
Serial opcode. Opcode field is serial. Other fields are quad/dual.
0x3 : ALL_QUAD_DUAL
All quad/dual. All fields of the command are in quad/dual format.
End of enumeration elements list.
FRAMEFORM : This field controls the opcode and address fields.
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x1 : OPCODE
Opcode. Opcode only, no address.
0x2 : OPCODE_1_BYTE
Opcode one byte. Opcode, least-significant byte of address.
0x3 : OPCODE_2_BYTES
Opcode two bytes. Opcode, 2 least-significant bytes of address.
0x4 : OPCODE_3_BYTES
Opcode three bytes. Opcode, 3 least-significant bytes of address.
0x5 : OPCODE_4_BYTES
Opcode four bytes. Opcode, 4 bytes of address.
0x6 : NO_OPCODE_3_BYTES
No opcode three bytes. No opcode, 3 least-significant bytes of address.
0x7 : NO_OPCODE_4_BYTES
No opcode, 4 bytes of address.
End of enumeration elements list.
OPCODE : The opcode of the command (not used for some FRAMEFORM values).
bits : 24 - 31 (8 bit)
access : read-write
SPIFI status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCINIT : This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register.
bits : 0 - 0 (1 bit)
access : read-write
CMD : This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash.
bits : 1 - 1 (1 bit)
access : read-write
RESET : Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register.
bits : 4 - 4 (1 bit)
access : read-write
INTRQ : This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS.
bits : 5 - 5 (1 bit)
access : read-write
SPIFI command register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATALEN : Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field.
bits : 0 - 13 (14 bit)
access : read-write
POLL : This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the DATALEN field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising CS. The end-of-command interrupt can be enabled to inform software when this occurs
bits : 14 - 14 (1 bit)
access : read-write
DOUT : If the DATALEN field is not zero, this bit controls the direction of the data:
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Input from serial flash.
0x1 : OUTPUT
Output to serial flash.
End of enumeration elements list.
INTLEN : This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes.
bits : 16 - 18 (3 bit)
access : read-write
FIELDFORM : This field controls how the fields of the command are sent.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : ALL_SERIAL
All serial. All fields of the command are serial.
0x1 : QUAD_DUAL_DATA
Quad/dual data. Data field is quad/dual, other fields are serial.
0x2 : SERIAL_OPCODE
Serial opcode. Opcode field is serial. Other fields are quad/dual.
0x3 : ALL_QUAD_DUAL
All quad/dual. All fields of the command are in quad/dual format.
End of enumeration elements list.
FRAMEFORM : This field controls the opcode and address fields.
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
0x1 : OPCODE
Opcode. Opcode only, no address.
0x2 : OPCODE_1_BYTE
Opcode one byte. Opcode, least significant byte of address.
0x3 : OPCODE_2_BYTES
Opcode two bytes. Opcode, two least significant bytes of address.
0x4 : OPCODE_3_BYTES
Opcode three bytes. Opcode, three least significant bytes of address.
0x5 : OPCODE_4_BYTES
Opcode four bytes. Opcode, 4 bytes of address.
0x6 : NO_OPCODE_3_BYTES
No opcode three bytes. No opcode, 3 least significant bytes of address.
0x7 : NO_OPCODE_4_BYTES
No opcode four bytes. No opcode, 4 bytes of address.
End of enumeration elements list.
OPCODE : The opcode of the command (not used for some FRAMEFORM values).
bits : 24 - 31 (8 bit)
access : read-write
SPIFI address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address.
bits : 0 - 31 (32 bit)
access : read-write
SPIFI intermediate data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDATA : Value of intermediate bytes.
bits : 0 - 31 (32 bit)
access : read-write
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