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address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0INT : Interrupt flag for match channel 0.
bits : 0 - 0 (1 bit)
access : read-write
MR1INT : Interrupt flag for match channel 1.
bits : 1 - 1 (1 bit)
access : read-write
MR2INT : Interrupt flag for match channel 2.
bits : 2 - 2 (1 bit)
access : read-write
MR3INT : Interrupt flag for match channel 3.
bits : 3 - 3 (1 bit)
access : read-write
CR0INT : Interrupt flag for capture channel 0 event.
bits : 4 - 4 (1 bit)
access : read-write
CR1INT : Interrupt flag for capture channel 1 event.
bits : 5 - 5 (1 bit)
access : read-write
CR2INT : Interrupt flag for capture channel 2 event.
bits : 6 - 6 (1 bit)
access : read-write
CR3INT : Interrupt flag for capture channel 3 event.
bits : 7 - 7 (1 bit)
access : read-write
Prescale Counter
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCVAL : Prescale counter value.
bits : 0 - 31 (32 bit)
access : read-write
Match Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MR0I : Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
bits : 0 - 0 (1 bit)
access : read-write
MR0R : Reset on MR0: the TC will be reset if MR0 matches it.
bits : 1 - 1 (1 bit)
access : read-write
MR0S : Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
bits : 2 - 2 (1 bit)
access : read-write
MR1I : Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
bits : 3 - 3 (1 bit)
access : read-write
MR1R : Reset on MR1: the TC will be reset if MR1 matches it.
bits : 4 - 4 (1 bit)
access : read-write
MR1S : Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
bits : 5 - 5 (1 bit)
access : read-write
MR2I : Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
bits : 6 - 6 (1 bit)
access : read-write
MR2R : Reset on MR2: the TC will be reset if MR2 matches it.
bits : 7 - 7 (1 bit)
access : read-write
MR2S : Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
bits : 8 - 8 (1 bit)
access : read-write
MR3I : Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
bits : 9 - 9 (1 bit)
access : read-write
MR3R : Reset on MR3: the TC will be reset if MR3 matches it.
bits : 10 - 10 (1 bit)
access : read-write
MR3S : Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
bits : 11 - 11 (1 bit)
access : read-write
MR0RL : Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).
bits : 24 - 24 (1 bit)
access : read-write
MR1RL : Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).
bits : 25 - 25 (1 bit)
access : read-write
MR2RL : Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).
bits : 26 - 26 (1 bit)
access : read-write
MR3RL : Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).
bits : 27 - 27 (1 bit)
access : read-write
Match Shadow Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHADOWW : Timer counter match shadow value.
bits : 0 - 31 (32 bit)
access : read-write
Match Shadow Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHADOWW : Timer counter match shadow value.
bits : 0 - 31 (32 bit)
access : read-write
Match Shadow Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHADOWW : Timer counter match shadow value.
bits : 0 - 31 (32 bit)
access : read-write
Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAP0RE : Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 0 - 0 (1 bit)
access : read-write
CAP0FE : Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 1 - 1 (1 bit)
access : read-write
CAP0I : Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
bits : 2 - 2 (1 bit)
access : read-write
CAP1RE : Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 3 - 3 (1 bit)
access : read-write
CAP1FE : Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 4 - 4 (1 bit)
access : read-write
CAP1I : Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
bits : 5 - 5 (1 bit)
access : read-write
CAP2RE : Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 6 - 6 (1 bit)
access : read-write
CAP2FE : Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 7 - 7 (1 bit)
access : read-write
CAP2I : Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
bits : 8 - 8 (1 bit)
access : read-write
CAP3RE : Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 9 - 9 (1 bit)
access : read-write
CAP3FE : Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.
bits : 10 - 10 (1 bit)
access : read-write
CAP3I : Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
bits : 11 - 11 (1 bit)
access : read-write
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
access : read-write
External Match Register. The EMR controls the match function and the external match pins.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
bits : 0 - 0 (1 bit)
access : read-write
EM1 : External Match 1. This bit reflects the state of output MAT1, whether or not this output is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
bits : 1 - 1 (1 bit)
access : read-write
EM2 : External Match 2. This bit reflects the state of output MAT2, whether or not this output is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
bits : 2 - 2 (1 bit)
access : read-write
EM3 : External Match 3. This bit reflects the state of output MAT3, whether or not this output is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
bits : 3 - 3 (1 bit)
access : read-write
EMC0 : External Match Control 0. Determines the functionality of External Match 0.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DO_NOTHING
Do Nothing.
0x1 : CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
0x2 : SET
Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC1 : External Match Control 1. Determines the functionality of External Match 1.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : DO_NOTHING
Do Nothing.
0x1 : CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
0x2 : SET
Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC2 : External Match Control 2. Determines the functionality of External Match 2.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DO_NOTHING
Do Nothing.
0x1 : CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
0x2 : SET
Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
End of enumeration elements list.
EMC3 : External Match Control 3. Determines the functionality of External Match 3.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DO_NOTHING
Do Nothing.
0x1 : CLEAR
Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
0x2 : SET
Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
0x3 : TOGGLE
Toggle. Toggle the corresponding External Match bit/output.
End of enumeration elements list.
Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Counter enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled.The counters are disabled.
0x1 : ENABLED
Enabled. The Timer Counter and Prescale Counter are enabled.
End of enumeration elements list.
CRST : Counter reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. Do nothing.
0x1 : ENABLED
Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
End of enumeration elements list.
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
access : read-only
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
access : read-write
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTMODE : Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TIMER
Timer Mode. Incremented every rising APB bus clock edge.
0x1 : COUNTER_RISING_EDGE
Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.
0x2 : COUNTER_FALLING_EDGE
Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
0x3 : COUNTER_DUAL_EDGE
Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
End of enumeration elements list.
CINSEL : Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : CHANNEL_0
Channel 0. CAPn.0 for CTIMERn
0x1 : CHANNEL_1
Channel 1. CAPn.1 for CTIMERn
0x2 : CHANNEL_2
Channel 2. CAPn.2 for CTIMERn
0x3 : CHANNEL_3
Channel 3. CAPn.3 for CTIMERn
End of enumeration elements list.
ENCC : Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.
bits : 4 - 4 (1 bit)
access : read-write
SELCC : Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : CHANNEL_0_RISING
Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x1 : CHANNEL_0_FALLING
Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
0x2 : CHANNEL_1_RISING
Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x3 : CHANNEL_1_FALLING
Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
0x4 : CHANNEL_2_RISING
Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
0x5 : CHANNEL_2_FALLING
Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
End of enumeration elements list.
PWM Control Register. The PWMCON enables PWM mode for the external match pins.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMEN0 : PWM mode enable for channel0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MATCH
Match. CTIMERn_MAT0 is controlled by EM0.
0x1 : PWM
PWM. PWM mode is enabled for CTIMERn_MAT0.
End of enumeration elements list.
PWMEN1 : PWM mode enable for channel1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : MATCH
Match. CTIMERn_MAT01 is controlled by EM1.
0x1 : PWM
PWM. PWM mode is enabled for CTIMERn_MAT1.
End of enumeration elements list.
PWMEN2 : PWM mode enable for channel2.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : MATCH
Match. CTIMERn_MAT2 is controlled by EM2.
0x1 : PWM
PWM. PWM mode is enabled for CTIMERn_MAT2.
End of enumeration elements list.
PWMEN3 : PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MATCH
Match. CTIMERn_MAT3 is controlled by EM3.
0x1 : PWM
PWM. PWM mode is enabled for CT132Bn_MAT3.
End of enumeration elements list.
Timer Counter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCVAL : Timer counter value.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
access : read-only
Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Timer counter match value.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
access : read-only
Prescale Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRVAL : Prescale counter value.
bits : 0 - 31 (32 bit)
access : read-write
Match Shadow Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHADOWW : Timer counter match shadow value.
bits : 0 - 31 (32 bit)
access : read-write
Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAP : Timer counter capture value.
bits : 0 - 31 (32 bit)
access : read-only
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