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SMARTCARD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected

Registers

DLL

RBR

THR

LSR

SCR

OSR

DLM

IER

SCICTRL

FCR

IIR

LCR


DLL

Divisor Latch LSB
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : RBR_THR_DLL
reset_Mask : 0x0

DLL DLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLLSB

DLLSB : The SCIn Divisor Latch LSB Register, along with the SCInDLM register, determines the baud rate of the SCIn.
bits : 0 - 7 (8 bit)
access : read-write


RBR

Receiver Buffer Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : RBR_THR_DLL
reset_Mask : 0x0

RBR RBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR

RBR : The SCIn Receiver Buffer Register contains the oldest received byte in the SCIn Rx FIFO.
bits : 0 - 7 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : RBR_THR_DLL
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THR

THR : Writing to the SCIn Transmit Holding Register causes the data to be stored in the SCIn transmit FIFO.
bits : 0 - 7 (8 bit)
access : write-only


LSR

Line Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LSR LSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR OE PE FE THRE TEMT RXFE

RDR : Receiver Data Ready.
bits : 0 - 0 (1 bit)
access : read-only

OE : Overrun Error.
bits : 1 - 1 (1 bit)
access : read-only

PE : Parity Error.
bits : 2 - 2 (1 bit)
access : read-only

FE : Framing Error.
bits : 3 - 3 (1 bit)
access : read-only

THRE : Transmitter Holding Register Empty.
bits : 5 - 5 (1 bit)
access : read-only

TEMT : Transmitter Empty.
bits : 6 - 6 (1 bit)
access : read-only

RXFE : Error in RX FIFO.
bits : 7 - 7 (1 bit)
access : read-only


SCR

Scratch Pad Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD

PAD : A readable, writable byte.
bits : 0 - 7 (8 bit)
access : read-write


OSR

Oversampling register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSR OSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSFRAC OSINT FDINT

OSFRAC : Fractional part of the oversampling ratio, in units of 1/8th of an input clock period.
bits : 1 - 3 (3 bit)
access : read-write

OSINT : Integer part of the oversampling ratio, minus 1.
bits : 4 - 7 (4 bit)
access : read-write

FDINT : These bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3.
bits : 8 - 14 (7 bit)
access : read-write


DLM

Divisor Latch MSB
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DLM_IER
reset_Mask : 0x0

DLM DLM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLMSB

DLMSB : The SCIn Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the SCIn.
bits : 0 - 7 (8 bit)
access : read-write


IER

Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DLM_IER
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBRIE THREIE RXIE

RBRIE : RBR Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write

THREIE : THRE Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-write

RXIE : RX Line Status Interrupt Enable.
bits : 2 - 2 (1 bit)
access : read-write


SCICTRL

Smart Card Interface control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCICTRL SCICTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCIEN NACKDIS PROTSEL TXRETRY GUARDTIME

SCIEN : Smart Card Interface Enable.
bits : 0 - 0 (1 bit)
access : read-write

NACKDIS : NACK response disable.
bits : 1 - 1 (1 bit)
access : read-write

PROTSEL : Protocol selection as defined in the ISO7816-3 standard.
bits : 2 - 2 (1 bit)
access : read-write

TXRETRY : Maximum number of retransmissions in case of a negative acknowledge (protocol T=0).
bits : 5 - 7 (3 bit)
access : read-write

GUARDTIME : Extra guard time.
bits : 8 - 15 (8 bit)
access : read-write


FCR

FIFO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : IIR_FCR
reset_Mask : 0x0

FCR FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOEN RXFIFORES TXFIFORES DMAMODE RXTRIGLVL

FIFOEN : FIFO Enable.
bits : 0 - 0 (1 bit)
access : write-only

RXFIFORES : RX FIFO Reset.
bits : 1 - 1 (1 bit)
access : write-only

TXFIFORES : TX FIFO Reset.
bits : 2 - 2 (1 bit)
access : write-only

DMAMODE : DMA Mode Select.
bits : 3 - 3 (1 bit)
access : write-only

RXTRIGLVL : RX Trigger Level.
bits : 6 - 7 (2 bit)
access : write-only


IIR

Interrupt ID Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : IIR_FCR
reset_Mask : 0x0

IIR IIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSTATUS INTID FIFOENABLE

INTSTATUS : Interrupt status.
bits : 0 - 0 (1 bit)
access : read-only

INTID : Interrupt identification.
bits : 1 - 3 (3 bit)
access : read-only

FIFOENABLE : Copies of SCInFCR[0].
bits : 6 - 7 (2 bit)
access : read-only


LCR

Line Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR LCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS SBS PE PS DLAB

WLS : Word Length Select.
bits : 0 - 1 (2 bit)
access : read-write

SBS : Stop Bit Select.
bits : 2 - 2 (1 bit)
access : read-write

PE : Parity Enable.
bits : 3 - 3 (1 bit)
access : read-write

PS : Parity Select.
bits : 4 - 5 (2 bit)
access : read-write

DLAB : Divisor Latch Access Bit.
bits : 7 - 7 (1 bit)
access : read-write



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