\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
Async peripheral reset control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTIMER3 : Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write
CTIMER4 : Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write
Async peripheral clock control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTIMER3 : Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write
CTIMER4 : Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write
Set bits in ASYNCAPBCLKCTRL
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACLK_SET : Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Clear bits in ASYNCAPBCLKCTRL
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACLK_CLR : Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Async APB clock source select A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Clock source for asynchronous clock source selector A
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x2 : AUDIO_PLL_CLOCK
Audio PLL clock.(AUDPLL_BYPASS)
0x3 : FC6_FCLK
fc6 fclk (fc6_fclk)
End of enumeration elements list.
Set bits in ASYNCPRESETCTRL
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ARST_SET : Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Clear bits in ASYNCPRESETCTRL
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ARST_CLR : Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
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