\n

SHA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

MEMCTRL

ALIAS[4]

DIGEST[2]

ALIAS[5]

MEMADDR

DIGEST[3]

ALIAS[6]

DIGEST[4]

DIGEST[5]

INDATA

DIGEST[6]

DIGEST[7]

STATUS

ALIAS[0]

ALIAS[1]

INTENSET

DIGEST[0]

ALIAS[2]

INTENCLR

DIGEST[1]

ALIAS[3]


CTRL

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE NEW DMA

MODE : This field is used to select the operational mode of SHA block.
bits : 0 - 1 (2 bit)
access : read-write

NEW : When this bit is set, a new hash operation is started.
bits : 4 - 4 (1 bit)
access : read-write

DMA : When this bit is set, the DMA is used to fill INDATA.
bits : 8 - 8 (1 bit)
access : read-write


MEMCTRL

Memory Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMCTRL MEMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER COUNT

MASTER : This field is used to enable SHA block as AHB bus master.
bits : 0 - 0 (1 bit)
access : read-write

COUNT : This field indicates the number of 512-bit blocks to copy starting at MEMADDR.
bits : 16 - 26 (11 bit)
access : read-write


ALIAS[4]

Alias register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[4] ALIAS[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


DIGEST[2]

Digest register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[2] DIGEST[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


ALIAS[5]

Alias register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[5] ALIAS[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


MEMADDR

Memory Address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMADDR MEMADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR

BASEADDR : This field indicates the base address in Internal Flash, SRAM0, SRAMX, or SPIFI to start copying from.
bits : 0 - 31 (32 bit)
access : read-write


DIGEST[3]

Digest register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[3] DIGEST[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


ALIAS[6]

Alias register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[6] ALIAS[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


DIGEST[4]

Digest register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[4] DIGEST[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


DIGEST[5]

Digest register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[5] DIGEST[5] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


INDATA

Input Data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INDATA INDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


DIGEST[6]

Digest register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[6] DIGEST[6] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


DIGEST[7]

Digest register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[7] DIGEST[7] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


STATUS

Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITING DIGEST ERROR

WAITING : This field indicates if the block is waiting for more data to process.
bits : 0 - 0 (1 bit)
access : read-write

DIGEST : This field indicates if a DIGEST is ready and waiting and there is no active next block that has already started.
bits : 1 - 1 (1 bit)
access : read-write

ERROR : This field indicates if an error has occurred.
bits : 2 - 2 (1 bit)
access : read-write


ALIAS[0]

Alias register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[0] ALIAS[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


ALIAS[1]

Alias register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[1] ALIAS[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


INTENSET

Interrupt Enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITING DIGEST ERROR

WAITING : This field indicates if interrupt should be enabled when waiting for input data.
bits : 0 - 0 (1 bit)
access : read-write

DIGEST : This field indicates if interrupt is generated when Digest is ready (completed a Hash or completed a full sequence).
bits : 1 - 1 (1 bit)
access : read-write

ERROR : This field indicates if interrupt is generated on an ERROR (as defined in STAT register).
bits : 2 - 2 (1 bit)
access : read-write


DIGEST[0]

Digest register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[0] DIGEST[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


ALIAS[2]

Alias register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[2] ALIAS[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only


INTENCLR

Interrupt Clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITING DIGEST ERROR

WAITING : Writing a 1 clears the interrupt enabled by the INTENSET register.
bits : 0 - 0 (1 bit)
access : write-only

DIGEST : Writing a 1 clears the interrupt enabled by the INTENSET register.
bits : 1 - 1 (1 bit)
access : write-only

ERROR : Writing a 1 clears the interrupt enabled by the INTENSET register.
bits : 2 - 2 (1 bit)
access : write-only


DIGEST[1]

Digest register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGEST[1] DIGEST[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGEST

DIGEST : This field contains one word of the Digest.
bits : 0 - 31 (32 bit)
access : read-only


ALIAS[3]

Alias register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALIAS[3] ALIAS[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : In this field the next word is written in little-endian format.
bits : 0 - 31 (32 bit)
access : write-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.