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ASYNC_SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ASYNCPRESETCTRL

ASYNCAPBCLKCTRL

ASYNCAPBCLKCTRLSET

ASYNCAPBCLKCTRLCLR

ASYNCAPBCLKSELA

ASYNCPRESETCTRLSET

ASYNCPRESETCTRLCLR


ASYNCPRESETCTRL

Async peripheral reset control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNCPRESETCTRL ASYNCPRESETCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTIMER3 CTIMER4

CTIMER3 : Standard counter/timer CTIMER3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write

CTIMER4 : Standard counter/timer CTIMER4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write


ASYNCAPBCLKCTRL

Async peripheral clock control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNCAPBCLKCTRL ASYNCAPBCLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTIMER3 CTIMER4

CTIMER3 : Controls the clock for CTIMER3. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write

CTIMER4 : Controls the clock for CTIMER4. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write


ASYNCAPBCLKCTRLSET

Set bits in ASYNCAPBCLKCTRL
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNCAPBCLKCTRLSET ASYNCAPBCLKCTRLSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACLK_SET

ACLK_SET : Writing ones to this register sets the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


ASYNCAPBCLKCTRLCLR

Clear bits in ASYNCAPBCLKCTRL
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNCAPBCLKCTRLCLR ASYNCAPBCLKCTRLCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACLK_CLR

ACLK_CLR : Writing ones to this register clears the corresponding bit or bits in the ASYNCAPBCLKCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCAPBCLKCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


ASYNCAPBCLKSELA

Async APB clock source select A
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNCAPBCLKSELA ASYNCAPBCLKSELA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Clock source for asynchronous clock source selector A
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : MAIN_CLOCK

Main clock (main_clk)

0x1 : FRO_12_MHZ

FRO 12 MHz (fro_12m)

0x2 : AUDIO_PLL_CLOCK

Audio PLL clock.(AUDPLL_BYPASS)

0x3 : FC6_FCLK

fc6 fclk (fc6_fclk)

End of enumeration elements list.


ASYNCPRESETCTRLSET

Set bits in ASYNCPRESETCTRL
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNCPRESETCTRLSET ASYNCPRESETCTRLSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARST_SET

ARST_SET : Writing ones to this register sets the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only


ASYNCPRESETCTRLCLR

Clear bits in ASYNCPRESETCTRL
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNCPRESETCTRLCLR ASYNCPRESETCTRLCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARST_CLR

ARST_CLR : Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented. Bits that do not correspond to defined bits in ASYNCPRESETCTRL are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only



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