ID

CFG1

CFG2

STAT

DIV

SECCHANNEL[0]-PCFG1

SECCHANNEL[0]-PCFG2

SECCHANNEL[0]-PSTAT

SECCHANNEL[1]-SECCHANNEL[0]-PCFG1

SECCHANNEL[1]-SECCHANNEL[0]-PCFG2

SECCHANNEL[1]-SECCHANNEL[0]-PSTAT

SECCHANNEL[2]-SECCHANNEL[1]-SECCHANNEL[0]-PCFG1

SECCHANNEL[2]-SECCHANNEL[1]-SECCHANNEL[0]-PCFG2

SECCHANNEL[2]-SECCHANNEL[1]-SECCHANNEL[0]-PSTAT

FIFOCFG

FIFOSTAT

FIFOTRIG

FIFOINTENSET

FIFOINTENCLR

FIFOINTSTAT

FIFOWR

FIFOWR48H

FIFORD

FIFORD48H

FIFORDNOPOP

FIFORD48HNOPOP

Aperture : Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
bits : 0 - 7 (8 bit)
access : read-only

Minor_Rev : Minor revision of module implementation, starting at 0.
bits : 8 - 11 (4 bit)
access : read-only

Major_Rev : Major revision of module implementation, starting at 0.
bits : 12 - 15 (4 bit)
access : read-only

ID : Unique module identifier for this IP block.
bits : 16 - 31 (16 bit)
access : read-only

MAINENABLE : Main enable for I 2S function in this Flexcomm
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATAPAUSE : Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAIRCOUNT : Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSTSLVCFG : Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIGHTLOW : Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEFTJUST : Left Justify data.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ONECHANNEL : Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMDATA : PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCK_POL : SCK polarity.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WS_POL : WS polarity.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATALEN : Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length
bits : 16 - 20 (5 bit)
access : read-write

FRAMELEN : Frame Length, minus 1 encoded, defines the number of clocks and data bits in the frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger than DATALEN in order for the WS pulse to be generated correctly.
bits : 0 - 8 (9 bit)
access : read-write

POSITION : Data Position. Defines the location within the frame of the data for this channel pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION defines the location of data in both the left phase and right phase, starting one clock after the WS edge. In other modes, POSITION defines the location of data within the entire frame. ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
bits : 16 - 24 (9 bit)
access : read-write

BUSY : Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLVFRMERR : Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

LR : Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATAPAUSED : Data Paused status flag. Applies to all I2S channels
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DIV : This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is divided by 4,096.
bits : 0 - 11 (12 bit)
access : read-write

PAIRENABLE : Enable for this channel pair..
bits : 0 - 0 (1 bit)
access : read-write

ONECHANNEL : Single channel mode.
bits : 10 - 10 (1 bit)
access : read-write

POSITION : Data Position.
bits : 16 - 24 (9 bit)
access : read-write

BUSY : Busy status for this channel pair.
bits : 0 - 0 (1 bit)
access : read-write

SLVFRMERR : Save Frame Error flag.
bits : 1 - 1 (1 bit)
access : read-write

LR : Left/Right indication.
bits : 2 - 2 (1 bit)
access : read-write

DATAPAUSED : Data Paused status flag.
bits : 3 - 3 (1 bit)
access : read-only

PAIRENABLE : Enable for this channel pair..
bits : 0 - 0 (1 bit)
access : read-write

ONECHANNEL : Single channel mode.
bits : 10 - 10 (1 bit)
access : read-write

POSITION : Data Position.
bits : 16 - 24 (9 bit)
access : read-write

BUSY : Busy status for this channel pair.
bits : 0 - 0 (1 bit)
access : read-write

SLVFRMERR : Save Frame Error flag.
bits : 1 - 1 (1 bit)
access : read-write

LR : Left/Right indication.
bits : 2 - 2 (1 bit)
access : read-write

DATAPAUSED : Data Paused status flag.
bits : 3 - 3 (1 bit)
access : read-only

PAIRENABLE : Enable for this channel pair..
bits : 0 - 0 (1 bit)
access : read-write

ONECHANNEL : Single channel mode.
bits : 10 - 10 (1 bit)
access : read-write

POSITION : Data Position.
bits : 16 - 24 (9 bit)
access : read-write

BUSY : Busy status for this channel pair.
bits : 0 - 0 (1 bit)
access : read-write

SLVFRMERR : Save Frame Error flag.
bits : 1 - 1 (1 bit)
access : read-write

LR : Left/Right indication.
bits : 2 - 2 (1 bit)
access : read-write

DATAPAUSED : Data Paused status flag.
bits : 3 - 3 (1 bit)
access : read-only

ENABLETX : Enable the transmit FIFO.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENABLERX : Enable the receive FIFO.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXI2SE0 : Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PACK48 : Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SIZE : FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
bits : 4 - 5 (2 bit)
access : read-only

DMATX : DMA configuration for transmit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMARX : DMA configuration for receive.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKETX : Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKERX : Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMPTYTX : Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
bits : 16 - 16 (1 bit)
access : read-write

EMPTYRX : Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
bits : 17 - 17 (1 bit)
access : read-write

POPDBG : Pop FIFO for debug reads.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXERR : TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is needed. Cleared by writing a 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write

RXERR : RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
bits : 1 - 1 (1 bit)
access : read-write

PERINT : Peripheral interrupt. When 1, this indicates that the peripheral function has asserted an interrupt. The details can be found by reading the peripheral's STAT register.
bits : 3 - 3 (1 bit)
access : read-only

TXEMPTY : Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
bits : 4 - 4 (1 bit)
access : read-only

TXNOTFULL : Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be written. When 0, the transmit FIFO is full and another write would cause it to overflow.
bits : 5 - 5 (1 bit)
access : read-only

RXNOTEMPTY : Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
bits : 6 - 6 (1 bit)
access : read-only

RXFULL : Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to prevent the peripheral from causing an overflow.
bits : 7 - 7 (1 bit)
access : read-only

TXLVL : Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be 0.
bits : 8 - 12 (5 bit)
access : read-only

RXLVL : Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be 1.
bits : 16 - 20 (5 bit)
access : read-only

TXLVLENA : Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXLVLENA : Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXLVL : Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX FIFO level decreases to 15 entries (is no longer full).
bits : 8 - 11 (4 bit)
access : read-write

RXLVL : Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).
bits : 16 - 19 (4 bit)
access : read-write

TXERR : Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXERR : Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXLVL : Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXLVL : Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 0 - 0 (1 bit)
access : read-write

RXERR : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 1 - 1 (1 bit)
access : read-write

TXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 2 - 2 (1 bit)
access : read-write

RXLVL : Writing one clears the corresponding bits in the FIFOINTENSET register.
bits : 3 - 3 (1 bit)
access : read-write

TXERR : TX FIFO error.
bits : 0 - 0 (1 bit)
access : read-only

RXERR : RX FIFO error.
bits : 1 - 1 (1 bit)
access : read-only

TXLVL : Transmit FIFO level interrupt.
bits : 2 - 2 (1 bit)
access : read-only

RXLVL : Receive FIFO level interrupt.
bits : 3 - 3 (1 bit)
access : read-only

PERINT : Peripheral interrupt.
bits : 4 - 4 (1 bit)
access : read-only

TXDATA : Transmit data to the FIFO. The number of bits used depends on configuration details.
bits : 0 - 31 (32 bit)
access : write-only

TXDATA : Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
bits : 0 - 23 (24 bit)
access : write-only

RXDATA : Received data from the FIFO. The number of bits used depends on configuration details.
bits : 0 - 31 (32 bit)
access : read-only

RXDATA : Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
bits : 0 - 23 (24 bit)
access : read-only

RXDATA : Received data from the FIFO.
bits : 0 - 31 (32 bit)
access : read-only

RXDATA : Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
bits : 0 - 23 (24 bit)
access : read-only