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address_offset : 0x0 Bytes (0x0)
size : 0x604 byte (0x0)
mem_usage : registers
protection : not protected
Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop back mode.
bits : 4 - 4 (1 bit)
access : read-write
TX : Control of transmit pin.
bits : 5 - 6 (2 bit)
access : read-write
RX : Monitors the actual value of the CAN_RXD.
bits : 7 - 7 (1 bit)
access : read-write
CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization.
bits : 0 - 0 (1 bit)
access : read-write
CCE : Configuration change enable.
bits : 1 - 1 (1 bit)
access : read-write
ASM : Restricted operational mode.
bits : 2 - 2 (1 bit)
access : read-write
CSA : Clock Stop Acknowledge.
bits : 3 - 3 (1 bit)
access : read-write
CSR : Clock Stop Request.
bits : 4 - 4 (1 bit)
access : read-write
MON : Bus monitoring mode.
bits : 5 - 5 (1 bit)
access : read-write
DAR : Disable automatic retransmission.
bits : 6 - 6 (1 bit)
access : read-write
TEST : Test mode enable.
bits : 7 - 7 (1 bit)
access : read-write
PXHD : Protocol exception handling disable.
bits : 12 - 12 (1 bit)
access : read-write
EFBI : Edge filtering during bus integration.
bits : 13 - 13 (1 bit)
access : read-write
TXP : Transmit pause.
bits : 14 - 14 (1 bit)
access : read-write
Nominal Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTSEG2 : Nominal time segment after sample point.
bits : 0 - 6 (7 bit)
access : read-write
NTSEG1 : Nominal time segment before sample point.
bits : 8 - 15 (8 bit)
access : read-write
NBRP : Nominal bit rate prescaler.
bits : 16 - 24 (9 bit)
access : read-write
NSJW : Nominal (re)synchronization jump width.
bits : 25 - 31 (7 bit)
access : read-write
Timestamp Counter Configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp select.
bits : 0 - 1 (2 bit)
access : read-write
TCP : Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times.
bits : 16 - 19 (4 bit)
access : read-write
CAN Message RAM Base Address
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BA : Base address for the message RAM in the chip memory map.
bits : 16 - 31 (16 bit)
access : read-write
Timestamp Counter Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp counter.
bits : 0 - 15 (16 bit)
access : read-write
Timeout Counter Configuration
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable timeout counter.
bits : 0 - 0 (1 bit)
access : read-write
TOS : Timeout select.
bits : 1 - 2 (2 bit)
access : read-write
TOP : Timeout period.
bits : 16 - 31 (16 bit)
access : read-write
Timeout Counter Value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout counter.
bits : 0 - 15 (16 bit)
access : read-only
Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit error counter.
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive error counter.
bits : 8 - 14 (7 bit)
access : read-only
RP : Receive error passive.
bits : 15 - 15 (1 bit)
access : read-only
CEL : CAN error logging.
bits : 16 - 23 (8 bit)
access : read-only
External Timestamp Counter Configuration
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETCP : External timestamp prescaler value.
bits : 0 - 10 (11 bit)
access : read-write
ETCE : External timestamp counter enable.
bits : 31 - 31 (1 bit)
access : read-write
Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last error code.
bits : 0 - 2 (3 bit)
access : read-only
ACT : Activity.
bits : 3 - 4 (2 bit)
access : read-only
EP : Error Passive.
bits : 5 - 5 (1 bit)
access : read-only
EW : Warning status.
bits : 6 - 6 (1 bit)
access : read-only
BO : Bus Off Status.
bits : 7 - 7 (1 bit)
access : read-only
PXE : Protocol exception event.
bits : 14 - 14 (1 bit)
access : read-only
TDCV : Transmitter delay compensation value.
bits : 16 - 22 (7 bit)
access : read-only
Transmitter Delay Compensator Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter delay compensation filter window length.
bits : 0 - 6 (7 bit)
access : read-write
TDCO : Transmitter delay compensation offset.
bits : 8 - 14 (7 bit)
access : read-write
Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 new message.
bits : 0 - 0 (1 bit)
access : read-write
RF0W : Rx FIFO 0 watermark reached.
bits : 1 - 1 (1 bit)
access : read-write
RF0F : Rx FIFO 0 full.
bits : 2 - 2 (1 bit)
access : read-write
RF0L : Rx FIFO 0 message lost.
bits : 3 - 3 (1 bit)
access : read-write
RF1N : Rx FIFO 1 new message.
bits : 4 - 4 (1 bit)
access : read-write
RF1W : Rx FIFO 1 watermark reached.
bits : 5 - 5 (1 bit)
access : read-write
RF1F : Rx FIFO 1 full.
bits : 6 - 6 (1 bit)
access : read-write
RF1L : Rx FIFO 1 message lost.
bits : 7 - 7 (1 bit)
access : read-write
HPM : High priority message.
bits : 8 - 8 (1 bit)
access : read-write
TC : Transmission completed.
bits : 9 - 9 (1 bit)
access : read-write
TCF : Transmission cancellation finished.
bits : 10 - 10 (1 bit)
access : read-write
TFE : Tx FIFO empty.
bits : 11 - 11 (1 bit)
access : read-write
TEFN : Tx event FIFO new entry.
bits : 12 - 12 (1 bit)
access : read-write
TEFW : Tx event FIFO watermark reached.
bits : 13 - 13 (1 bit)
access : read-write
TEFF : Tx event FIFO full.
bits : 14 - 14 (1 bit)
access : read-write
TEFL : Tx event FIFO element lost.
bits : 15 - 15 (1 bit)
access : read-write
TSW : Timestamp wraparound.
bits : 16 - 16 (1 bit)
access : read-write
MRAF : Message RAM access failure.
bits : 17 - 17 (1 bit)
access : read-write
TOO : Timeout occurred.
bits : 18 - 18 (1 bit)
access : read-write
DRX : Message stored in dedicated Rx buffer.
bits : 19 - 19 (1 bit)
access : read-write
BEC : Bit error corrected.
bits : 20 - 20 (1 bit)
access : read-write
BEU : Bit error uncorrected.
bits : 21 - 21 (1 bit)
access : read-write
ELO : Error logging overflow.
bits : 22 - 22 (1 bit)
access : read-write
EP : Error passive.
bits : 23 - 23 (1 bit)
access : read-write
EW : Warning status.
bits : 24 - 24 (1 bit)
access : read-write
BO : Bus_Off Status.
bits : 25 - 25 (1 bit)
access : read-write
WDI : Watchdog interrupt.
bits : 26 - 26 (1 bit)
access : read-write
PEA : Protocol error in arbitration phase.
bits : 27 - 27 (1 bit)
access : read-write
PED : Protocol error in data phase.
bits : 28 - 28 (1 bit)
access : read-write
ARA : Access to reserved address.
bits : 29 - 29 (1 bit)
access : read-write
Interrupt Enable
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 new message interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write
RF0WE : Rx FIFO 0 watermark reached interrupt enable.
bits : 1 - 1 (1 bit)
access : read-write
RF0FE : Rx FIFO 0 full interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write
RF0LE : Rx FIFO 0 message lost interrupt enable.
bits : 3 - 3 (1 bit)
access : read-write
RF1NE : Rx FIFO 1 new message interrupt enable.
bits : 4 - 4 (1 bit)
access : read-write
RF1WE : Rx FIFO 1 watermark reached interrupt enable.
bits : 5 - 5 (1 bit)
access : read-write
RF1FE : Rx FIFO 1 full interrupt enable.
bits : 6 - 6 (1 bit)
access : read-write
RF1LE : Rx FIFO 1 message lost interrupt enable.
bits : 7 - 7 (1 bit)
access : read-write
HPME : High priority message interrupt enable.
bits : 8 - 8 (1 bit)
access : read-write
TCE : Transmission completed interrupt enable.
bits : 9 - 9 (1 bit)
access : read-write
TCFE : Transmission cancellation finished interrupt enable.
bits : 10 - 10 (1 bit)
access : read-write
TFEE : Tx FIFO empty interrupt enable.
bits : 11 - 11 (1 bit)
access : read-write
TEFNE : Tx event FIFO new entry interrupt enable.
bits : 12 - 12 (1 bit)
access : read-write
TEFWE : Tx event FIFO watermark reached interrupt enable.
bits : 13 - 13 (1 bit)
access : read-write
TEFFE : Tx event FIFO full interrupt enable.
bits : 14 - 14 (1 bit)
access : read-write
TEFLE : Tx event FIFO element lost interrupt enable.
bits : 15 - 15 (1 bit)
access : read-write
TSWE : Timestamp wraparound interrupt enable.
bits : 16 - 16 (1 bit)
access : read-write
MRAFE : Message RAM access failure interrupt enable.
bits : 17 - 17 (1 bit)
access : read-write
TOOE : Timeout occurred interrupt enable.
bits : 18 - 18 (1 bit)
access : read-write
DRXE : Message stored in dedicated Rx buffer interrupt enable.
bits : 19 - 19 (1 bit)
access : read-write
BECE : Bit error corrected interrupt enable.
bits : 20 - 20 (1 bit)
access : read-write
BEUE : Bit error uncorrected interrupt enable.
bits : 21 - 21 (1 bit)
access : read-write
ELOE : Error logging overflow interrupt enable.
bits : 22 - 22 (1 bit)
access : read-write
EPE : Error passive interrupt enable.
bits : 23 - 23 (1 bit)
access : read-write
EWE : Warning status interrupt enable.
bits : 24 - 24 (1 bit)
access : read-write
BOE : Bus_Off Status interrupt enable.
bits : 25 - 25 (1 bit)
access : read-write
WDIE : Watchdog interrupt enable.
bits : 26 - 26 (1 bit)
access : read-write
PEAE : Protocol error in arbitration phase interrupt enable.
bits : 27 - 27 (1 bit)
access : read-write
PEDE : Protocol error in data phase interrupt enable.
bits : 28 - 28 (1 bit)
access : read-write
ARAE : Access to reserved address interrupt enable.
bits : 29 - 29 (1 bit)
access : read-write
Interrupt Line Select
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 new message interrupt line.
bits : 0 - 0 (1 bit)
access : read-write
RF0WL : Rx FIFO 0 watermark reached interrupt line.
bits : 1 - 1 (1 bit)
access : read-write
RF0FL : Rx FIFO 0 full interrupt line.
bits : 2 - 2 (1 bit)
access : read-write
RF0LL : Rx FIFO 0 message lost interrupt line.
bits : 3 - 3 (1 bit)
access : read-write
RF1NL : Rx FIFO 1 new message interrupt line.
bits : 4 - 4 (1 bit)
access : read-write
RF1WL : Rx FIFO 1 watermark reached interrupt line.
bits : 5 - 5 (1 bit)
access : read-write
RF1FL : Rx FIFO 1 full interrupt line.
bits : 6 - 6 (1 bit)
access : read-write
RF1LL : Rx FIFO 1 message lost interrupt line.
bits : 7 - 7 (1 bit)
access : read-write
HPML : High priority message interrupt line.
bits : 8 - 8 (1 bit)
access : read-write
TCL : Transmission completed interrupt line.
bits : 9 - 9 (1 bit)
access : read-write
TCFL : Transmission cancellation finished interrupt line.
bits : 10 - 10 (1 bit)
access : read-write
TFEL : Tx FIFO empty interrupt line.
bits : 11 - 11 (1 bit)
access : read-write
TEFNL : Tx event FIFO new entry interrupt line.
bits : 12 - 12 (1 bit)
access : read-write
TEFWL : Tx event FIFO watermark reached interrupt line.
bits : 13 - 13 (1 bit)
access : read-write
TEFFL : Tx event FIFO full interrupt line.
bits : 14 - 14 (1 bit)
access : read-write
TEFLL : Tx event FIFO element lost interrupt line.
bits : 15 - 15 (1 bit)
access : read-write
TSWL : Timestamp wraparound interrupt line.
bits : 16 - 16 (1 bit)
access : read-write
MRAFL : Message RAM access failure interrupt line.
bits : 17 - 17 (1 bit)
access : read-write
TOOL : Timeout occurred interrupt line.
bits : 18 - 18 (1 bit)
access : read-write
DRXL : Message stored in dedicated Rx buffer interrupt line.
bits : 19 - 19 (1 bit)
access : read-write
BECL : Bit error corrected interrupt line.
bits : 20 - 20 (1 bit)
access : read-write
BEUL : Bit error uncorrected interrupt line.
bits : 21 - 21 (1 bit)
access : read-write
ELOL : Error logging overflow interrupt line.
bits : 22 - 22 (1 bit)
access : read-write
EPL : Error passive interrupt line.
bits : 23 - 23 (1 bit)
access : read-write
EWL : Warning status interrupt line.
bits : 24 - 24 (1 bit)
access : read-write
BOL : Bus_Off Status interrupt line.
bits : 25 - 25 (1 bit)
access : read-write
WDIL : Watchdog interrupt line.
bits : 26 - 26 (1 bit)
access : read-write
PEAL : Protocol error in arbitration phase interrupt line.
bits : 27 - 27 (1 bit)
access : read-write
PEDL : Protocol error in data phase interrupt line.
bits : 28 - 28 (1 bit)
access : read-write
ARAL : Access to reserved address interrupt line.
bits : 29 - 29 (1 bit)
access : read-write
Interrupt Line Enable
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable interrupt line 0.
bits : 0 - 0 (1 bit)
access : read-write
EINT1 : Enable interrupt line 1.
bits : 1 - 1 (1 bit)
access : read-write
External Timestamp Counter Value
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETSC : External timestamp counter.
bits : 0 - 15 (16 bit)
access : read-write
Global Filter Configuration
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject remote frames extended.
bits : 0 - 0 (1 bit)
access : read-write
RRFS : Reject remote frames standard.
bits : 1 - 1 (1 bit)
access : read-write
ANFE : Accept non-matching frames extended.
bits : 2 - 3 (2 bit)
access : read-write
ANFS : Accept non-matching frames standard.
bits : 4 - 5 (2 bit)
access : read-write
Standard ID Filter Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter list standard start address.
bits : 2 - 15 (14 bit)
access : read-write
LSS : List size standard 0 = No standard message ID filter.
bits : 16 - 23 (8 bit)
access : read-write
Extended ID Filter Configuration
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter list extended start address.
bits : 2 - 15 (14 bit)
access : read-write
LSE : List size extended 0 = No extended message ID filter.
bits : 16 - 23 (8 bit)
access : read-write
Extended ID AND Mask
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID mask.
bits : 0 - 28 (29 bit)
access : read-write
High Priority Message Status
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer index.
bits : 0 - 5 (6 bit)
access : read-only
MSI : Message storage indicator.
bits : 6 - 7 (2 bit)
access : read-only
FIDX : Filter index.
bits : 8 - 14 (7 bit)
access : read-only
FLST : Filter list.
bits : 15 - 15 (1 bit)
access : read-only
New Data 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND : New Data.
bits : 0 - 31 (32 bit)
access : read-write
New Data 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND : New Data.
bits : 0 - 31 (32 bit)
access : read-write
Rx FIFO 0 Configuration
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 start address.
bits : 2 - 15 (14 bit)
access : read-write
F0S : Rx FIFO 0 size.
bits : 16 - 22 (7 bit)
access : read-write
F0WM : Rx FIFO 0 watermark 0 = Watermark interrupt disabled.
bits : 24 - 30 (7 bit)
access : read-write
F0OM : FIFO 0 operation mode.
bits : 31 - 31 (1 bit)
access : read-write
Rx FIFO 0 Status
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 fill level.
bits : 0 - 6 (7 bit)
access : read-write
F0GI : Rx FIFO 0 get index.
bits : 8 - 13 (6 bit)
access : read-write
F0PI : Rx FIFO 0 put index.
bits : 16 - 21 (6 bit)
access : read-write
F0F : Rx FIFO 0 full.
bits : 24 - 24 (1 bit)
access : read-write
RF0L : Rx FIFO 0 message lost.
bits : 25 - 25 (1 bit)
access : read-write
Rx FIFO 0 Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Rx FIFO 0 acknowledge index.
bits : 0 - 5 (6 bit)
access : read-write
Rx Buffer Configuration
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : Rx buffer start address.
bits : 2 - 15 (14 bit)
access : read-write
Rx FIFO 1 Configuration
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 start address.
bits : 2 - 15 (14 bit)
access : read-write
F1S : Rx FIFO 1 size 0 = No Rx FIFO 1.
bits : 16 - 22 (7 bit)
access : read-write
F1WM : Rx FIFO 1 watermark 0 = Watermark interrupt disabled.
bits : 24 - 30 (7 bit)
access : read-write
F1OM : FIFO 1 operation mode.
bits : 31 - 31 (1 bit)
access : read-write
Rx FIFO 1 Status
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 fill level.
bits : 0 - 6 (7 bit)
access : read-only
F1GI : Rx FIFO 1 get index.
bits : 8 - 13 (6 bit)
access : read-only
F1PI : Rx FIFO 1 put index.
bits : 16 - 21 (6 bit)
access : read-only
F1F : Rx FIFO 1 full.
bits : 24 - 24 (1 bit)
access : read-only
RF1L : Rx FIFO 1 message lost.
bits : 25 - 25 (1 bit)
access : read-only
Rx FIFO 1 Acknowledge
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 acknowledge index.
bits : 0 - 5 (6 bit)
access : read-write
Rx Buffer and FIFO Element Size Configuration
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 0 data field size.
bits : 0 - 2 (3 bit)
access : read-write
F1DS : Rx FIFO 1 data field size.
bits : 4 - 6 (3 bit)
access : read-write
RBDS : .
bits : 8 - 10 (3 bit)
access : read-write
Tx Buffer Configuration
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx buffers start address.
bits : 2 - 15 (14 bit)
access : read-write
NDTB : Number of dedicated transmit buffers 0 = No dedicated Tx buffers.
bits : 16 - 21 (6 bit)
access : read-write
TFQS : Transmit FIFO/queue size 0 = No tx FIFO/Queue.
bits : 24 - 29 (6 bit)
access : read-write
TFQM : Tx FIFO/queue mode.
bits : 30 - 30 (1 bit)
access : read-write
Tx FIFO/Queue Status
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFGI : Tx FIFO get index.
bits : 8 - 12 (5 bit)
access : read-write
TFQPI : Tx FIFO/queue put index.
bits : 16 - 20 (5 bit)
access : read-write
TFQF : Tx FIFO/queue full.
bits : 21 - 21 (1 bit)
access : read-write
Tx Buffer Element Size Configuration
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx buffer data field size.
bits : 0 - 2 (3 bit)
access : read-write
Tx Buffer Request Pending
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRP : Transmission request pending.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Add Request
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR : Add request.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Cancellation Request
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR : Cancellation request.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Transmission Occurred
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Transmission occurred.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Cancellation Finished
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO : Cancellation finished.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Transmission Interrupt Enable
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmission interrupt enable.
bits : 0 - 31 (32 bit)
access : read-write
Tx Buffer Cancellation Finished Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIE : Cancellation finished interrupt enable.
bits : 0 - 31 (32 bit)
access : read-write
Tx Event FIFO Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO start address.
bits : 2 - 15 (14 bit)
access : read-write
EFS : Event FIFO size 0 = Tx event FIFO disabled.
bits : 16 - 21 (6 bit)
access : read-write
EFWM : Event FIFO watermark 0 = Watermark interrupt disabled.
bits : 24 - 29 (6 bit)
access : read-write
Tx Event FIFO Status
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO fill level.
bits : 0 - 5 (6 bit)
access : read-only
EFGI : Event FIFO get index.
bits : 8 - 12 (5 bit)
access : read-only
EFPI : Event FIFO put index.
bits : 16 - 21 (6 bit)
access : read-only
EFF : Event FIFO full.
bits : 24 - 24 (1 bit)
access : read-only
TEFL : Tx event FIFO element lost.
bits : 25 - 25 (1 bit)
access : read-only
Tx Event FIFO Acknowledge
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO acknowledge index.
bits : 0 - 4 (5 bit)
access : read-write
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