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EMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x27C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CONTROL

DYNAMIC[0]-DYNAMICCONFIG

DYNAMIC[0]-DYNAMICRASCAS

DYNAMICCONTROL

STATIC[0]-STATICCONFIG

STATIC[0]-STATICWAITWEN

STATIC[0]-STATICWAITOEN

STATIC[0]-STATICWAITRD

STATIC[0]-STATICWAITPAGE

STATIC[0]-STATICWAITWR

STATIC[0]-STATICWAITTURN

DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

DYNAMICREFRESH

DYNAMICREADCONFIG

DYNAMICRP

DYNAMICRAS

DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

DYNAMICSREX

DYNAMICAPR

STATUS

DYNAMICDAL

STATIC[1]-STATIC[0]-STATICCONFIG

STATIC[1]-STATIC[0]-STATICWAITWEN

STATIC[1]-STATIC[0]-STATICWAITOEN

STATIC[1]-STATIC[0]-STATICWAITRD

STATIC[1]-STATIC[0]-STATICWAITPAGE

STATIC[1]-STATIC[0]-STATICWAITWR

STATIC[1]-STATIC[0]-STATICWAITTURN

DYNAMICWR

DYNAMICRC

DYNAMICRFC

DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

DYNAMICXSR

DYNAMICRRD

DYNAMICMRD

STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN

CONFIG

STATICEXTENDEDWAIT

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN


CONTROL

Controls operation of the memory controller
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E M L

E : EMC Enable.
bits : 0 - 0 (1 bit)
access : read-write

M : Address mirror.
bits : 1 - 1 (1 bit)
access : read-write

L : Low-power mode.
bits : 2 - 2 (1 bit)
access : read-write


DYNAMIC[0]-DYNAMICCONFIG

Configuration information for EMC_DYCSx
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[0]-DYNAMICCONFIG DYNAMIC[0]-DYNAMICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD AM0 AM1 B P

MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write

AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write

AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write

B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


DYNAMIC[0]-DYNAMICRASCAS

RAS and CAS latencies for EMC_DYCSx
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[0]-DYNAMICRASCAS DYNAMIC[0]-DYNAMICRASCAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAS CAS

RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write

CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write


DYNAMICCONTROL

Controls dynamic memory operation
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICCONTROL DYNAMICCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE CS SR MMC I

CE : Dynamic memory clock enable.
bits : 0 - 0 (1 bit)
access : read-write

CS : Dynamic memory clock control.
bits : 1 - 1 (1 bit)
access : read-write

SR : Self-refresh request, EMCSREFREQ.
bits : 2 - 2 (1 bit)
access : read-write

MMC : Memory clock control.
bits : 5 - 5 (1 bit)
access : read-write

I : SDRAM initialization.
bits : 7 - 8 (2 bit)
access : read-write


STATIC[0]-STATICCONFIG

Configuration for EMC_CSx
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICCONFIG STATIC[0]-STATICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW PM PC PB EW B P

MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write

PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write

PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write

PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write

EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write

B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


STATIC[0]-STATICWAITWEN

Delay from EMC_CSx to write enable
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITWEN STATIC[0]-STATICWAITWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWEN

WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[0]-STATICWAITOEN

Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITOEN STATIC[0]-STATICWAITOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITOEN

WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[0]-STATICWAITRD

Delay from EMC_CSx to a read access
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITRD STATIC[0]-STATICWAITRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITRD

WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write


STATIC[0]-STATICWAITPAGE

Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITPAGE STATIC[0]-STATICWAITPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITPAGE

WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[0]-STATICWAITWR

Delay from EMC_CSx to a write access
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITWR STATIC[0]-STATICWAITWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWR

WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[0]-STATICWAITTURN

Number of bus turnaround cycles EMC_CSx
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[0]-STATICWAITTURN STATIC[0]-STATICWAITTURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITTURN

WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

Configuration information for EMC_DYCSx
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD AM0 AM1 B P

MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write

AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write

AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write

B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

RAS and CAS latencies for EMC_DYCSx
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAS CAS

RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write

CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write


DYNAMICREFRESH

Configures dynamic memory refresh
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICREFRESH DYNAMICREFRESH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFRESH

REFRESH : Refresh timer.
bits : 0 - 10 (11 bit)
access : read-write


DYNAMICREADCONFIG

Configures dynamic memory read strategy
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICREADCONFIG DYNAMICREADCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD

RD : Read data strategy.
bits : 0 - 1 (2 bit)
access : read-write


DYNAMICRP

Precharge command period
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICRP DYNAMICRP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : Precharge command period.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMICRAS

Active to precharge command period
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICRAS DYNAMICRAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRAS

TRAS : Active to precharge command period.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

Configuration information for EMC_DYCSx
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD AM0 AM1 B P

MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write

AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write

AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write

B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

RAS and CAS latencies for EMC_DYCSx
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAS CAS

RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write

CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write


DYNAMICSREX

Self-refresh exit time
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICSREX DYNAMICSREX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSREX

TSREX : Self-refresh exit time.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMICAPR

Last-data-out to active command time
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICAPR DYNAMICAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAPR

TAPR : Last-data-out to active command time.
bits : 0 - 3 (4 bit)
access : read-write


STATUS

Provides EMC status information
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B S SA

B : Busy.
bits : 0 - 0 (1 bit)
access : read-only

S : Write buffer status.
bits : 1 - 1 (1 bit)
access : read-only

SA : Self-refresh acknowledge.
bits : 2 - 2 (1 bit)
access : read-only


DYNAMICDAL

Data-in to active command time
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICDAL DYNAMICDAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDAL

TDAL : Data-in to active command.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICCONFIG

Configuration for EMC_CSx
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICCONFIG STATIC[1]-STATIC[0]-STATICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW PM PC PB EW B P

MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write

PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write

PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write

PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write

EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write

B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITWEN

Delay from EMC_CSx to write enable
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITWEN STATIC[1]-STATIC[0]-STATICWAITWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWEN

WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITOEN

Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITOEN STATIC[1]-STATIC[0]-STATICWAITOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITOEN

WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITRD

Delay from EMC_CSx to a read access
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITRD STATIC[1]-STATIC[0]-STATICWAITRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITRD

WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITPAGE

Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITPAGE STATIC[1]-STATIC[0]-STATICWAITPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITPAGE

WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITWR

Delay from EMC_CSx to a write access
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITWR STATIC[1]-STATIC[0]-STATICWAITWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWR

WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[1]-STATIC[0]-STATICWAITTURN

Number of bus turnaround cycles EMC_CSx
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[1]-STATIC[0]-STATICWAITTURN STATIC[1]-STATIC[0]-STATICWAITTURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITTURN

WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMICWR

Write recovery time
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICWR DYNAMICWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWR

TWR : Write recovery time.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMICRC

Selects the active to active command period
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICRC DYNAMICRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRC

TRC : Active to active command period.
bits : 0 - 4 (5 bit)
access : read-write


DYNAMICRFC

Selects the auto-refresh period
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICRFC DYNAMICRFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRFC

TRFC : Auto-refresh period and auto-refresh to active command period.
bits : 0 - 4 (5 bit)
access : read-write


DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG

Configuration information for EMC_DYCSx
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD AM0 AM1 B P

MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write

AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write

AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write

B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS

RAS and CAS latencies for EMC_DYCSx
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAS CAS

RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write

CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write


DYNAMICXSR

Time for exit self-refresh to active command
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICXSR DYNAMICXSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSR

TXSR : Exit self-refresh to active command time.
bits : 0 - 4 (5 bit)
access : read-write


DYNAMICRRD

Latency for active bank A to active bank B
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICRRD DYNAMICRRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRRD

TRRD : Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
bits : 0 - 3 (4 bit)
access : read-write


DYNAMICMRD

Time for load mode register to active command
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DYNAMICMRD DYNAMICMRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRD

TMRD : Load mode register to active command time.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG

Configuration for EMC_CSx
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW PM PC PB EW B P

MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write

PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write

PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write

PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write

EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write

B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN

Delay from EMC_CSx to write enable
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWEN

WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN

Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITOEN

WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD

Delay from EMC_CSx to a read access
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITRD

WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE

Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITPAGE

WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR

Delay from EMC_CSx to a write access
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWR

WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN

Number of bus turnaround cycles EMC_CSx
address_offset : 0x678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITTURN

WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write


CONFIG

Configures operation of the memory controller
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM CLKR

EM : Endian mode.
bits : 0 - 0 (1 bit)
access : read-write

CLKR : This bit must contain 0 for proper operation of the EMC.
bits : 8 - 8 (1 bit)
access : read-write


STATICEXTENDEDWAIT

Time for long static memory read and write transfers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATICEXTENDEDWAIT STATICEXTENDEDWAIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTENDEDWAIT

EXTENDEDWAIT : Extended wait time out.
bits : 0 - 9 (10 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG

Configuration for EMC_CSx
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MW PM PC PB EW B P

MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write

PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write

PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write

PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write

EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write

B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write

P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN

Delay from EMC_CSx to write enable
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWEN

WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN

Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITOEN

WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD

Delay from EMC_CSx to a read access
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITRD

WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE

Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITPAGE

WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR

Delay from EMC_CSx to a write access
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITWR

WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write


STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN

Number of bus turnaround cycles EMC_CSx
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITTURN

WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write



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