\n
address_offset : 0x0 Bytes (0x0)
size : 0x27C byte (0x0)
mem_usage : registers
protection : not protected
DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG
DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS
DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG
DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS
STATIC[1]-STATIC[0]-STATICCONFIG
STATIC[1]-STATIC[0]-STATICWAITWEN
STATIC[1]-STATIC[0]-STATICWAITOEN
STATIC[1]-STATIC[0]-STATICWAITRD
STATIC[1]-STATIC[0]-STATICWAITPAGE
STATIC[1]-STATIC[0]-STATICWAITWR
STATIC[1]-STATIC[0]-STATICWAITTURN
DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICCONFIG
DYNAMIC[3]-DYNAMIC[2]-DYNAMIC[1]-DYNAMIC[0]-DYNAMICRASCAS
STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR
STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICCONFIG
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWEN
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITOEN
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITRD
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITPAGE
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITWR
STATIC[3]-STATIC[2]-STATIC[1]-STATIC[0]-STATICWAITTURN
Controls operation of the memory controller
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
E : EMC Enable.
bits : 0 - 0 (1 bit)
access : read-write
M : Address mirror.
bits : 1 - 1 (1 bit)
access : read-write
L : Low-power mode.
bits : 2 - 2 (1 bit)
access : read-write
Configuration information for EMC_DYCSx
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write
AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write
AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write
B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
RAS and CAS latencies for EMC_DYCSx
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write
CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write
Controls dynamic memory operation
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CE : Dynamic memory clock enable.
bits : 0 - 0 (1 bit)
access : read-write
CS : Dynamic memory clock control.
bits : 1 - 1 (1 bit)
access : read-write
SR : Self-refresh request, EMCSREFREQ.
bits : 2 - 2 (1 bit)
access : read-write
MMC : Memory clock control.
bits : 5 - 5 (1 bit)
access : read-write
I : SDRAM initialization.
bits : 7 - 8 (2 bit)
access : read-write
Configuration for EMC_CSx
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write
PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write
PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write
PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write
EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write
B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
Delay from EMC_CSx to write enable
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx to a read access
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write
Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write
Delay from EMC_CSx to a write access
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write
Number of bus turnaround cycles EMC_CSx
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write
Configuration information for EMC_DYCSx
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write
AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write
AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write
B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
RAS and CAS latencies for EMC_DYCSx
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write
CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write
Configures dynamic memory refresh
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFRESH : Refresh timer.
bits : 0 - 10 (11 bit)
access : read-write
Configures dynamic memory read strategy
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD : Read data strategy.
bits : 0 - 1 (2 bit)
access : read-write
Precharge command period
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRP : Precharge command period.
bits : 0 - 3 (4 bit)
access : read-write
Active to precharge command period
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRAS : Active to precharge command period.
bits : 0 - 3 (4 bit)
access : read-write
Configuration information for EMC_DYCSx
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write
AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write
AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write
B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
RAS and CAS latencies for EMC_DYCSx
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write
CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write
Self-refresh exit time
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSREX : Self-refresh exit time.
bits : 0 - 3 (4 bit)
access : read-write
Last-data-out to active command time
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAPR : Last-data-out to active command time.
bits : 0 - 3 (4 bit)
access : read-write
Provides EMC status information
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
B : Busy.
bits : 0 - 0 (1 bit)
access : read-only
S : Write buffer status.
bits : 1 - 1 (1 bit)
access : read-only
SA : Self-refresh acknowledge.
bits : 2 - 2 (1 bit)
access : read-only
Data-in to active command time
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDAL : Data-in to active command.
bits : 0 - 3 (4 bit)
access : read-write
Configuration for EMC_CSx
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write
PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write
PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write
PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write
EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write
B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
Delay from EMC_CSx to write enable
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx to a read access
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write
Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write
Delay from EMC_CSx to a write access
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write
Number of bus turnaround cycles EMC_CSx
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write
Write recovery time
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWR : Write recovery time.
bits : 0 - 3 (4 bit)
access : read-write
Selects the active to active command period
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRC : Active to active command period.
bits : 0 - 4 (5 bit)
access : read-write
Selects the auto-refresh period
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRFC : Auto-refresh period and auto-refresh to active command period.
bits : 0 - 4 (5 bit)
access : read-write
Configuration information for EMC_DYCSx
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : Memory device.
bits : 3 - 4 (2 bit)
access : read-write
AM0 : See Table 933.
bits : 7 - 12 (6 bit)
access : read-write
AM1 : See Table 933.
bits : 14 - 14 (1 bit)
access : read-write
B : Buffer enable.
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
RAS and CAS latencies for EMC_DYCSx
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAS : RAS latency (active to read/write delay).
bits : 0 - 1 (2 bit)
access : read-write
CAS : CAS latency.
bits : 8 - 9 (2 bit)
access : read-write
Time for exit self-refresh to active command
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSR : Exit self-refresh to active command time.
bits : 0 - 4 (5 bit)
access : read-write
Latency for active bank A to active bank B
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRRD : Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles.
bits : 0 - 3 (4 bit)
access : read-write
Time for load mode register to active command
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRD : Load mode register to active command time.
bits : 0 - 3 (4 bit)
access : read-write
Configuration for EMC_CSx
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write
PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write
PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write
PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write
EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write
B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
Delay from EMC_CSx to write enable
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx to a read access
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write
Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write
Delay from EMC_CSx to a write access
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write
Number of bus turnaround cycles EMC_CSx
address_offset : 0x678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write
Configures operation of the memory controller
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM : Endian mode.
bits : 0 - 0 (1 bit)
access : read-write
CLKR : This bit must contain 0 for proper operation of the EMC.
bits : 8 - 8 (1 bit)
access : read-write
Time for long static memory read and write transfers
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTENDEDWAIT : Extended wait time out.
bits : 0 - 9 (10 bit)
access : read-write
Configuration for EMC_CSx
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MW : Memory width.
bits : 0 - 1 (2 bit)
access : read-write
PM : Page mode.
bits : 3 - 3 (1 bit)
access : read-write
PC : Chip select polarity.
bits : 6 - 6 (1 bit)
access : read-write
PB : Byte lane state.
bits : 7 - 7 (1 bit)
access : read-write
EW : Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers.
bits : 8 - 8 (1 bit)
access : read-write
B : Buffer enable [2].
bits : 19 - 19 (1 bit)
access : read-write
P : Write protect.
bits : 20 - 20 (1 bit)
access : read-write
Delay from EMC_CSx to write enable
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWEN : Wait write enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx or address change, whichever is later, to output enable
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITOEN : Wait output enable.
bits : 0 - 3 (4 bit)
access : read-write
Delay from EMC_CSx to a read access
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITRD : .
bits : 0 - 4 (5 bit)
access : read-write
Delay for asynchronous page mode sequential accesses for EMC_CSx
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITPAGE : Asynchronous page mode read after the first read wait states.
bits : 0 - 4 (5 bit)
access : read-write
Delay from EMC_CSx to a write access
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITWR : Write wait states.
bits : 0 - 4 (5 bit)
access : read-write
Number of bus turnaround cycles EMC_CSx
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITTURN : Bus turn-around cycles.
bits : 0 - 3 (4 bit)
access : read-write
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