Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x550 byte (0x0)
mem_usage : registers
protection : not protected
EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
EV[8]-EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[8]-EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
EV[9]-EV[8]-EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[9]-EV[8]-EV[7]-EV[6]-EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
OUT[8]-OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[8]-OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
OUT[9]-OUT[8]-OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
OUT[9]-OUT[8]-OUT[7]-OUT[6]-OUT[5]-OUT[4]-OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
SCT configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNIFY : SCT operation
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DUAL_COUNTER
The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
0x1 : UNIFIED_COUNTER
The SCT operates as a unified 32-bit counter.
End of enumeration elements list.
CLKMODE : SCT clock mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : SYSTEM_CLOCK_MODE
System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
0x1 : SAMPLED_SYSTEM_CLOCK_MODE
Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
0x2 : SCT_INPUT_CLOCK_MODE
SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
0x3 : ASYNCHRONOUS_MODE
Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.
End of enumeration elements list.
CKSEL : SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : INPUT_0_RISING_EDGES
Rising edges on input 0.
0x1 : INPUT_0_FALLING_EDGE
Falling edges on input 0.
0x2 : INPUT_1_RISING_EDGES
Rising edges on input 1.
0x3 : INPUT_1_FALLING_EDGE
Falling edges on input 1.
0x4 : INPUT_2_RISING_EDGES
Rising edges on input 2.
0x5 : INPUT_2_FALLING_EDGE
Falling edges on input 2.
0x6 : INPUT_3_RISING_EDGES
Rising edges on input 3.
0x7 : INPUT_3_FALLING_EDGE
Falling edges on input 3.
0x8 : INPUT_4_RISING_EDGES
Rising edges on input 4.
0x9 : INPUT_4_FALLING_EDGE
Falling edges on input 4.
0xA : INPUT_5_RISING_EDGES
Rising edges on input 5.
0xB : INPUT_5_FALLING_EDGE
Falling edges on input 5.
0xC : INPUT_6_RISING_EDGES
Rising edges on input 6.
0xD : INPUT_6_FALLING_EDGE
Falling edges on input 6.
0xE : INPUT_7_RISING_EDGES
Rising edges on input 7.
0xF : INPUT_7_FALLING_EDGE
Falling edges on input 7.
End of enumeration elements list.
NORELOAD_L : A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
bits : 7 - 7 (1 bit)
access : read-write
NORELOAD_H : A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
bits : 8 - 8 (1 bit)
access : read-write
INSYNC : Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
bits : 9 - 12 (4 bit)
access : read-write
AUTOLIMIT_L : A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
bits : 17 - 17 (1 bit)
access : read-write
AUTOLIMIT_H : A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
bits : 18 - 18 (1 bit)
access : read-write
SCT stop event select register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPMSK_L : If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
STOPMSK_H : If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture register of capture channel
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
CAPn_L : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
bits : 0 - 15 (16 bit)
access : read-write
CAPn_H : When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
bits : 16 - 31 (16 bit)
access : read-write
SCT match value register of match channels
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAP_MATCH
reset_Mask : 0x0
MATCHn_L : When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
bits : 0 - 15 (16 bit)
access : read-write
MATCHn_H : When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x1278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x127C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT start event select register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTMSK_L : If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
STARTMSK_H : If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0x1430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x1434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x15A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x15AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT event state register 0
address_offset : 0x18E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x18E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT output 0 set register
address_offset : 0x1950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x1954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x1C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x1C24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT output 0 set register
address_offset : 0x1E78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x1E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x1F68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT capture control register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT capture control register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
CAPCONn_L : If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
CAPCONn_H : If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT match reload value register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CAPCTRL_MATCHREL
reset_Mask : 0x0
RELOADn_L : When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 0 - 15 (16 bit)
access : read-write
RELOADn_H : When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
bits : 16 - 31 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0x23A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x23AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0x28E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x28E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0x2E20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x2E24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT output 0 set register
address_offset : 0x3368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x336C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOWN_L : This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
bits : 0 - 0 (1 bit)
access : read-write
STOP_L : When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
bits : 1 - 1 (1 bit)
access : read-write
HALT_L : When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
bits : 2 - 2 (1 bit)
access : read-write
CLRCTR_L : Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
bits : 3 - 3 (1 bit)
access : read-write
BIDIR_L : L or unified counter direction select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : UP
Up. The counter counts up to a limit condition, then is cleared to zero.
0x1 : UP_DOWN
Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
End of enumeration elements list.
PRE_L : Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
bits : 5 - 12 (8 bit)
access : read-write
DOWN_H : This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
bits : 16 - 16 (1 bit)
access : read-write
STOP_H : When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
bits : 17 - 17 (1 bit)
access : read-write
HALT_H : When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
bits : 18 - 18 (1 bit)
access : read-write
CLRCTR_H : Writing a 1 to this bit clears the H counter. This bit always reads as 0.
bits : 19 - 19 (1 bit)
access : read-write
BIDIR_H : Direction select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : UP
The H counter counts up to its limit condition, then is cleared to zero.
0x1 : UP_DOWN
The H counter counts up to its limit, then counts down to a limit condition or to 0.
End of enumeration elements list.
PRE_H : Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
bits : 21 - 28 (8 bit)
access : read-write
SCT counter register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR_L : When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
bits : 0 - 15 (16 bit)
access : read-write
CTR_H : When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
bits : 16 - 31 (16 bit)
access : read-write
SCT state register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE_L : State variable.
bits : 0 - 4 (5 bit)
access : read-write
STATE_H : State variable.
bits : 16 - 20 (5 bit)
access : read-write
SCT input register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AIN0 : Input 0 state. Input 0 state on the last SCT clock edge.
bits : 0 - 0 (1 bit)
access : read-only
AIN1 : Input 1 state. Input 1 state on the last SCT clock edge.
bits : 1 - 1 (1 bit)
access : read-only
AIN2 : Input 2 state. Input 2 state on the last SCT clock edge.
bits : 2 - 2 (1 bit)
access : read-only
AIN3 : Input 3 state. Input 3 state on the last SCT clock edge.
bits : 3 - 3 (1 bit)
access : read-only
AIN4 : Input 4 state. Input 4 state on the last SCT clock edge.
bits : 4 - 4 (1 bit)
access : read-only
AIN5 : Input 5 state. Input 5 state on the last SCT clock edge.
bits : 5 - 5 (1 bit)
access : read-only
AIN6 : Input 6 state. Input 6 state on the last SCT clock edge.
bits : 6 - 6 (1 bit)
access : read-only
AIN7 : Input 7 state. Input 7 state on the last SCT clock edge.
bits : 7 - 7 (1 bit)
access : read-only
AIN8 : Input 8 state. Input 8 state on the last SCT clock edge.
bits : 8 - 8 (1 bit)
access : read-only
AIN9 : Input 9 state. Input 9 state on the last SCT clock edge.
bits : 9 - 9 (1 bit)
access : read-only
AIN10 : Input 10 state. Input 10 state on the last SCT clock edge.
bits : 10 - 10 (1 bit)
access : read-only
AIN11 : Input 11 state. Input 11 state on the last SCT clock edge.
bits : 11 - 11 (1 bit)
access : read-only
AIN12 : Input 12 state. Input 12 state on the last SCT clock edge.
bits : 12 - 12 (1 bit)
access : read-only
AIN13 : Input 13 state. Input 13 state on the last SCT clock edge.
bits : 13 - 13 (1 bit)
access : read-only
AIN14 : Input 14 state. Input 14 state on the last SCT clock edge.
bits : 14 - 14 (1 bit)
access : read-only
AIN15 : Input 15 state. Input 15 state on the last SCT clock edge.
bits : 15 - 15 (1 bit)
access : read-only
SIN0 : Input 0 state. Input 0 state following the synchronization specified by INSYNC.
bits : 16 - 16 (1 bit)
access : read-only
SIN1 : Input 1 state. Input 1 state following the synchronization specified by INSYNC.
bits : 17 - 17 (1 bit)
access : read-only
SIN2 : Input 2 state. Input 2 state following the synchronization specified by INSYNC.
bits : 18 - 18 (1 bit)
access : read-only
SIN3 : Input 3 state. Input 3 state following the synchronization specified by INSYNC.
bits : 19 - 19 (1 bit)
access : read-only
SIN4 : Input 4 state. Input 4 state following the synchronization specified by INSYNC.
bits : 20 - 20 (1 bit)
access : read-only
SIN5 : Input 5 state. Input 5 state following the synchronization specified by INSYNC.
bits : 21 - 21 (1 bit)
access : read-only
SIN6 : Input 6 state. Input 6 state following the synchronization specified by INSYNC.
bits : 22 - 22 (1 bit)
access : read-only
SIN7 : Input 7 state. Input 7 state following the synchronization specified by INSYNC.
bits : 23 - 23 (1 bit)
access : read-only
SIN8 : Input 8 state. Input 8 state following the synchronization specified by INSYNC.
bits : 24 - 24 (1 bit)
access : read-only
SIN9 : Input 9 state. Input 9 state following the synchronization specified by INSYNC.
bits : 25 - 25 (1 bit)
access : read-only
SIN10 : Input 10 state. Input 10 state following the synchronization specified by INSYNC.
bits : 26 - 26 (1 bit)
access : read-only
SIN11 : Input 11 state. Input 11 state following the synchronization specified by INSYNC.
bits : 27 - 27 (1 bit)
access : read-only
SIN12 : Input 12 state. Input 12 state following the synchronization specified by INSYNC.
bits : 28 - 28 (1 bit)
access : read-only
SIN13 : Input 13 state. Input 13 state following the synchronization specified by INSYNC.
bits : 29 - 29 (1 bit)
access : read-only
SIN14 : Input 14 state. Input 14 state following the synchronization specified by INSYNC.
bits : 30 - 30 (1 bit)
access : read-only
SIN15 : Input 15 state. Input 15 state following the synchronization specified by INSYNC.
bits : 31 - 31 (1 bit)
access : read-only
SCT match/capture mode register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGMOD_L : Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.
bits : 0 - 15 (16 bit)
access : read-write
REGMOD_H : Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.
bits : 16 - 31 (16 bit)
access : read-write
SCT output register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT : Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output counter direction control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETCLR0 : Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR1 : Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR2 : Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR3 : Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR4 : Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR5 : Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR6 : Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR7 : Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR8 : Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR9 : Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR10 : Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR11 : Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR12 : Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR13 : Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR14 : Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SETCLR15 : Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : INDEPENDENT
Set and clear do not depend on the direction of any counter.
0x1 : L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x2 : H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
End of enumeration elements list.
SCT conflict resolution register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
O0RES : Effect of simultaneous set and clear on output 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR0 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O1RES : Effect of simultaneous set and clear on output 1.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR1 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O2RES : Effect of simultaneous set and clear on output 2.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output n (or set based on the SETCLR2 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O3RES : Effect of simultaneous set and clear on output 3.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR3 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O4RES : Effect of simultaneous set and clear on output 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR4 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O5RES : Effect of simultaneous set and clear on output 5.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR5 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O6RES : Effect of simultaneous set and clear on output 6.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR6 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O7RES : Effect of simultaneous set and clear on output 7.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output n (or set based on the SETCLR7 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O8RES : Effect of simultaneous set and clear on output 8.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR8 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O9RES : Effect of simultaneous set and clear on output 9.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR9 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O10RES : Effect of simultaneous set and clear on output 10.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR10 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O11RES : Effect of simultaneous set and clear on output 11.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR11 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O12RES : Effect of simultaneous set and clear on output 12.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR12 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O13RES : Effect of simultaneous set and clear on output 13.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR13 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O14RES : Effect of simultaneous set and clear on output 14.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR14 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
O15RES : Effect of simultaneous set and clear on output 15.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0 : NO_CHANGE
No change.
0x1 : SET
Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
0x2 : CLEAR
Clear output (or set based on the SETCLR15 field).
0x3 : TOGGLE_OUTPUT
Toggle output.
End of enumeration elements list.
SCT DMA request 0 register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_0 : If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
DRL0 : A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
bits : 30 - 30 (1 bit)
access : read-write
DRQ0 : This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
bits : 31 - 31 (1 bit)
access : read-write
SCT DMA request 1 register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_1 : If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
DRL1 : A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
bits : 30 - 30 (1 bit)
access : read-write
DRQ1 : This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
bits : 31 - 31 (1 bit)
access : read-write
SCT event state register 0
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT limit event select register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIMMSK_L : If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
LIMMSK_H : If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0x91C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT output 0 set register
address_offset : 0xA08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT halt event select register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTMSK_L : If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
HALTMSK_H : If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
bits : 16 - 31 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0xC30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT event interrupt enable register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN : The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 set register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT output 0 clear register
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR : A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
bits : 0 - 15 (16 bit)
access : read-write
SCT event flag register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLAG : Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event state register 0
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEMSKn : If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT event control register 0
address_offset : 0xF54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCHSEL : Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
bits : 0 - 3 (4 bit)
access : read-write
HEVENT : Select L/H counter. Do not set this bit if UNIFY = 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0x1 : H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
End of enumeration elements list.
OUTSEL : Input/output select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INPUT
Selects the inputs selected by IOSEL.
0x1 : OUTPUT
Selects the outputs selected by IOSEL.
End of enumeration elements list.
IOSEL : Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
bits : 6 - 9 (4 bit)
access : read-write
IOCOND : Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : LOW
LOW
0x1 : RISE
Rise
0x2 : FALL
Fall
0x3 : HIGH
HIGH
End of enumeration elements list.
COMBMODE : Selects how the specified match and I/O condition are used and combined.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : OR
OR. The event occurs when either the specified match or I/O condition occurs.
0x1 : MATCH
MATCH. Uses the specified match only.
0x2 : IO
IO. Uses the specified I/O condition only.
0x3 : AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
End of enumeration elements list.
STATELD : This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ADD
STATEV value is added into STATE (the carry-out is ignored).
0x1 : LOAD
STATEV value is loaded into STATE.
End of enumeration elements list.
STATEV : This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
bits : 15 - 19 (5 bit)
access : read-write
MATCHMEM : If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
bits : 20 - 20 (1 bit)
access : read-write
DIRECTION : Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
0 : DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0x1 : COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x2 : COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
End of enumeration elements list.
SCT conflict interrupt enable register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCEN : The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
SCT conflict flag register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCFLAG : Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
bits : 0 - 15 (16 bit)
access : read-write
BUSERRL : The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
bits : 30 - 30 (1 bit)
access : read-write
BUSERRH : The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
bits : 31 - 31 (1 bit)
access : read-write
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