Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20048 byte (0x0)
mem_usage : registers
protection : not protected
AHB multilayer matrix priority control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_ICODE : I-Code bus priority.
bits : 0 - 1 (2 bit)
access : read-write
PRI_DCODE : D-Code bus priority.
bits : 2 - 3 (2 bit)
access : read-write
PRI_SYS : System bus priority.
bits : 4 - 5 (2 bit)
access : read-write
PRI_DMA : DMA controller priority.
bits : 6 - 9 (4 bit)
access : read-write
PRI_ETH : Ethernet DMA priority.
bits : 10 - 11 (2 bit)
access : read-write
PRI_LCD : LCD DMA priority.
bits : 12 - 13 (2 bit)
access : read-write
PRI_USB0 : USB0 DMA priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_USB1 : USB1 DMA priority.
bits : 16 - 17 (2 bit)
access : read-write
PRI_SDIO : SDIO priority.
bits : 18 - 19 (2 bit)
access : read-write
PRI_MCAN1 : MCAN1 priority.
bits : 20 - 21 (2 bit)
access : read-write
PRI_MCAN2 : MCAN2 priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_SHA : SHA priority.
bits : 24 - 25 (2 bit)
access : read-write
Peripheral reset control n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_RST : Flash controller reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 7 - 7 (1 bit)
access : read-write
FMC_RST : Flash accelerator reset control. Note that the FMC must not be reset while executing from flash, and must be reconfigured after reset. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 8 - 8 (1 bit)
access : read-write
EEPROM_RST : EEPROM reset control.
bits : 9 - 9 (1 bit)
access : read-write
SPIFI_RST : SPIFI reset control.
bits : 10 - 10 (1 bit)
access : read-write
MUX_RST : Input mux reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 11 - 11 (1 bit)
access : read-write
IOCON_RST : IOCON reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write
GPIO0_RST : GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write
GPIO1_RST : GPIO1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 15 - 15 (1 bit)
access : read-write
GPIO2_RST : GPIO2 reset control.
bits : 16 - 16 (1 bit)
access : read-write
GPIO3_RST : GPIO3 reset control.
bits : 17 - 17 (1 bit)
access : read-write
PINT_RST : Pin interrupt (PINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 18 - 18 (1 bit)
access : read-write
GINT_RST : Grouped interrupt (GINT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 19 - 19 (1 bit)
access : read-write
DMA0_RST : DMA0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 20 - 20 (1 bit)
access : read-write
CRC_RST : CRC generator reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 21 - 21 (1 bit)
access : read-write
WWDT_RST : Watchdog timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 22 - 22 (1 bit)
access : read-write
ADC0_RST : ADC0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 27 - 27 (1 bit)
access : read-write
Peripheral reset control n
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRT_RST : Multi-rate timer (MRT) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 0 - 0 (1 bit)
access : read-write
SCT0_RST : State configurable timer 0 (SCT0) reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 2 - 2 (1 bit)
access : read-write
MCAN0_RST : 0 = Clear reset to this function.
bits : 7 - 7 (1 bit)
access : read-write
MCAN1_RST : 0 = Clear reset to this function.
bits : 8 - 8 (1 bit)
access : read-write
UTICK_RST : Micro-tick Timer reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 10 - 10 (1 bit)
access : read-write
FC0_RST : Flexcomm 0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 11 - 11 (1 bit)
access : read-write
FC1_RST : Flexcomm 1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 12 - 12 (1 bit)
access : read-write
FC2_RST : Flexcomm 2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 13 - 13 (1 bit)
access : read-write
FC3_RST : Flexcomm 3 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 14 - 14 (1 bit)
access : read-write
FC4_RST : Flexcomm 4 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 15 - 15 (1 bit)
access : read-write
FC5_RST : Flexcomm 5 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 16 - 16 (1 bit)
access : read-write
FC6_RST : Flexcomm 6 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 17 - 17 (1 bit)
access : read-write
FC7_RST : Flexcomm 7 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 18 - 18 (1 bit)
access : read-write
DMIC_RST : Digital microphone interface reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 19 - 19 (1 bit)
access : read-write
CTIMER2_RST : CTIMER2 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function
bits : 22 - 22 (1 bit)
access : read-write
USB0D_RST : USB0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 25 - 25 (1 bit)
access : read-write
CTIMER0_RST : CTIMER0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 26 - 26 (1 bit)
access : read-write
CTIMER1_RST : CTIMER1 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
bits : 27 - 27 (1 bit)
access : read-write
Flexcomm 0 clock source select
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Peripheral reset control n
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD_RST : LCD reset control.
bits : 2 - 2 (1 bit)
access : read-write
SDIO_RST : SDIO reset control.
bits : 3 - 3 (1 bit)
access : read-write
USB1H_RST : USB1 Host reset control.
bits : 4 - 4 (1 bit)
access : read-write
USB1D_RST : USB1 Device reset control.
bits : 5 - 5 (1 bit)
access : read-write
USB1RAM_RST : USB1 RAM reset control.
bits : 6 - 6 (1 bit)
access : read-write
EMC_RESET : EMC reset control.
bits : 7 - 7 (1 bit)
access : read-write
ETH_RST : Ethernet reset control.
bits : 8 - 8 (1 bit)
access : read-write
GPIO4_RST : GPIO4 reset control.
bits : 9 - 9 (1 bit)
access : read-write
GPIO5_RST : GPIO5 reset control.
bits : 10 - 10 (1 bit)
access : read-write
AES_RST : AES reset control.
bits : 11 - 11 (1 bit)
access : read-write
OTP_RST : OTP reset control.
bits : 12 - 12 (1 bit)
access : read-write
RNG_RST : RNG reset control.
bits : 13 - 13 (1 bit)
access : read-write
FC8_RST : Flexcomm 8 reset control.
bits : 14 - 14 (1 bit)
access : read-write
FC9_RST : Flexcomm 9 reset control.
bits : 15 - 15 (1 bit)
access : read-write
USB0HMR_RST : USB0 HOST master reset control.
bits : 16 - 16 (1 bit)
access : read-write
USB0HSL_RST : USB0 HOST slave reset control.
bits : 17 - 17 (1 bit)
access : read-write
SHA_RST : SHA reset control.
bits : 18 - 18 (1 bit)
access : read-write
SC0_RST : Smart card 0 reset control.
bits : 19 - 19 (1 bit)
access : read-write
SC1_RST : Smart card 1 reset control.
bits : 20 - 20 (1 bit)
access : read-write
Flexcomm 0 clock source select
address_offset : 0x130C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Set bits in STARTER
address_offset : 0x13E4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START_SET : Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
Clear bits in STARTER0
address_offset : 0x1444 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START_CLR : Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
Flexcomm 0 clock source select
address_offset : 0x15D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
POR captured value of port n
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIOPORCAP : State of PIOn_31 through PIOn_0 at power-on reset
bits : 0 - 31 (32 bit)
access : read-only
Flexcomm 0 clock source select
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Reset captured value of port n
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIORESCAP : State of PIOn_31 through PIOn_0 for resets other than POR.
bits : 0 - 31 (32 bit)
access : read-only
Flexcomm 0 clock source select
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Flexcomm 0 clock source select
address_offset : 0x1E44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
System reset status register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR : POR reset status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_POR_DETECTED
No POR detected
0x1 : POR_DETECTED
POR detected. Writing a one clears this reset.
End of enumeration elements list.
EXTRST : Status of the external RESET pin. External reset status
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NO_RESET_DETECTED
No reset event detected.
0x1 : RESET_DETECTED
Reset detected. Writing a one clears this reset.
End of enumeration elements list.
WDT : Status of the Watchdog reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NO_WDT_RESET_DETECTED
No WDT reset detected
0x1 : WDT_RESET_DETECTED
WDT reset detected. Writing a one clears this reset.
End of enumeration elements list.
BOD : Status of the Brown-out detect reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NO_BOD_RESET_DETECTED
No BOD reset detected
0x1 : BOD_RESET_DETECTED
BOD reset detected. Writing a one clears this reset.
End of enumeration elements list.
SYSRST : Status of the software system reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NO_SYSTEM_RESET_DETECTED
No System reset detected
0x1 : SYSTEM_RESET_DETECTED
System reset detected. Writing a one clears this reset.
End of enumeration elements list.
AHB Clock control n
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM : Enables the clock for the Boot ROM. 0 = Disable; 1 = Enable.
bits : 1 - 1 (1 bit)
access : read-write
SRAM1 : Enables the clock for SRAM1. 0 = Disable; 1 = Enable.
bits : 3 - 3 (1 bit)
access : read-write
SRAM2 : Enables the clock for SRAM2. 0 = Disable; 1 = Enable.
bits : 4 - 4 (1 bit)
access : read-write
SRAM3 : Enables the clock for SRAM3.
bits : 5 - 5 (1 bit)
access : read-write
FLASH : Enables the clock for the flash controller. 0 = Disable; 1 = Enable. This clock is needed for flash programming, not for flash read.
bits : 7 - 7 (1 bit)
access : read-write
FMC : Enables the clock for the Flash accelerator. 0 = Disable; 1 = Enable. This clock is needed if the flash is being read.
bits : 8 - 8 (1 bit)
access : read-write
EEPROM : Enables the clock for EEPROM.
bits : 9 - 9 (1 bit)
access : read-write
SPIFI : Enables the clock for the SPIFI. 0 = Disable; 1 = Enable.
bits : 10 - 10 (1 bit)
access : read-write
INPUTMUX : Enables the clock for the input muxes. 0 = Disable; 1 = Enable.
bits : 11 - 11 (1 bit)
access : read-write
IOCON : Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write
GPIO0 : Enables the clock for the GPIO0 port registers. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write
GPIO1 : Enables the clock for the GPIO1 port registers. 0 = Disable; 1 = Enable.
bits : 15 - 15 (1 bit)
access : read-write
GPIO2 : Enables the clock for the GPIO2 port registers.
bits : 16 - 16 (1 bit)
access : read-write
GPIO3 : Enables the clock for the GPIO3 port registers.
bits : 17 - 17 (1 bit)
access : read-write
PINT : Enables the clock for the pin interrupt block.0 = Disable; 1 = Enable.
bits : 18 - 18 (1 bit)
access : read-write
GINT : Enables the clock for the grouped pin interrupt block. 0 = Disable; 1 = Enable.
bits : 19 - 19 (1 bit)
access : read-write
DMA : Enables the clock for the DMA controller. 0 = Disable; 1 = Enable.
bits : 20 - 20 (1 bit)
access : read-write
CRC : Enables the clock for the CRC engine. 0 = Disable; 1 = Enable.
bits : 21 - 21 (1 bit)
access : read-write
WWDT : Enables the clock for the Watchdog Timer. 0 = Disable; 1 = Enable.
bits : 22 - 22 (1 bit)
access : read-write
RTC : Enables the bus clock for the RTC. 0 = Disable; 1 = Enable.
bits : 23 - 23 (1 bit)
access : read-write
ADC0 : Enables the clock for the ADC0 register interface.
bits : 27 - 27 (1 bit)
access : read-write
Brown-Out Detect control
address_offset : 0x20044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODRSTLEV : BOD reset level
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : LEVEL0
Level 0: 1.5 V
0x1 : LEVEL1
Level 1: 1.85 V
0x2 : LEVEL2
Level 2: 2.0 V
0x3 : LEVEL3
Level 3: 2.3 V
End of enumeration elements list.
BODRSTENA : BOD reset enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable reset function.
0x1 : ENABLE
Enable reset function.
End of enumeration elements list.
BODINTLEV : BOD interrupt level
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : LEVEL0
Level 0: 2.05 V
0x1 : LEVEL1
Level 1: 2.45 V
0x2 : LEVEL2
Level 2: 2.75 V
0x3 : LEVEL3
Level 3: 3.05 V
End of enumeration elements list.
BODINTENA : BOD interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable interrupt function.
0x1 : ENABLE
Enable interrupt function.
End of enumeration elements list.
BODRSTSTAT : BOD reset status. When 1, a BOD reset has occurred. Cleared by writing 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write
BODINTSTAT : BOD interrupt status. When 1, a BOD interrupt has occurred. Cleared by writing 1 to this bit.
bits : 7 - 7 (1 bit)
access : read-write
AHB Clock control n
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRT : Enables the clock for the Multi-Rate Timer.
bits : 0 - 0 (1 bit)
access : read-write
RIT : Enables the clock for the Repetitive Interrupt Timer.
bits : 1 - 1 (1 bit)
access : read-write
SCT0 : Enables the clock for SCT0.
bits : 2 - 2 (1 bit)
access : read-write
MCAN0 : Enables the clock for MCAN0.
bits : 7 - 7 (1 bit)
access : read-write
MCAN1 : Enables the clock for MCAN1.
bits : 8 - 8 (1 bit)
access : read-write
UTICK : Enables the clock for the Micro-tick Timer. 0 = Disable; 1 = Enable.
bits : 10 - 10 (1 bit)
access : read-write
FLEXCOMM0 : Enables the clock for Flexcomm 0. 0 = Disable; 1 = Enable.
bits : 11 - 11 (1 bit)
access : read-write
FLEXCOMM1 : Enables the clock for Flexcomm 1. 0 = Disable; 1 = Enable.
bits : 12 - 12 (1 bit)
access : read-write
FLEXCOMM2 : Enables the clock for Flexcomm 2. 0 = Disable; 1 = Enable.
bits : 13 - 13 (1 bit)
access : read-write
FLEXCOMM3 : Enables the clock for Flexcomm 3. 0 = Disable; 1 = Enable.
bits : 14 - 14 (1 bit)
access : read-write
FLEXCOMM4 : Enables the clock for Flexcomm 4. 0 = Disable; 1 = Enable.
bits : 15 - 15 (1 bit)
access : read-write
FLEXCOMM5 : Enables the clock for Flexcomm 5. 0 = Disable; 1 = Enable.
bits : 16 - 16 (1 bit)
access : read-write
FLEXCOMM6 : Enables the clock for Flexcomm 6. 0 = Disable; 1 = Enable.
bits : 17 - 17 (1 bit)
access : read-write
FLEXCOMM7 : Enables the clock for Flexcomm 7. 0 = Disable; 1 = Enable.
bits : 18 - 18 (1 bit)
access : read-write
DMIC : Enables the clock for the digital microphone interface. 0 = Disable; 1 = Enable.
bits : 19 - 19 (1 bit)
access : read-write
CTIMER2 : Enables the clock for CTIMER 2. 0 = Disable; 1 = Enable.
bits : 22 - 22 (1 bit)
access : read-write
USB0D : Enables the clock for the USB0 device interface. 0 = Disable; 1 = Enable.
bits : 25 - 25 (1 bit)
access : read-write
CTIMER0 : Enables the clock for timer CTIMER0. 0 = Disable; 1 = Enable.
bits : 26 - 26 (1 bit)
access : read-write
CTIMER1 : Enables the clock for timer CTIMER1. 0 = Disable; 1 = Enable.
bits : 27 - 27 (1 bit)
access : read-write
AHB Clock control n
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD : Enables the clock for the LCD interface.
bits : 2 - 2 (1 bit)
access : read-write
SDIO : Enables the clock for the SDIO interface.
bits : 3 - 3 (1 bit)
access : read-write
USB1H : Enables the clock for the USB1 host interface.
bits : 4 - 4 (1 bit)
access : read-write
USB1D : Enables the clock for the USB1 device interface.
bits : 5 - 5 (1 bit)
access : read-write
USB1RAM : Enables the clock for the USB1 RAM interface.
bits : 6 - 6 (1 bit)
access : read-write
EMC : Enables the clock for the EMC interface.
bits : 7 - 7 (1 bit)
access : read-write
ETH : Enables the clock for the ethernet interface.
bits : 8 - 8 (1 bit)
access : read-write
GPIO4 : Enables the clock for the GPIO4 interface.
bits : 9 - 9 (1 bit)
access : read-write
GPIO5 : Enables the clock for the GPIO5 interface.
bits : 10 - 10 (1 bit)
access : read-write
AES : Enables the clock for the AES interface.
bits : 11 - 11 (1 bit)
access : read-write
OTP : Enables the clock for the OTP interface.
bits : 12 - 12 (1 bit)
access : read-write
RNG : Enables the clock for the RNG interface.
bits : 13 - 13 (1 bit)
access : read-write
FLEXCOMM8 : Enables the clock for the Flexcomm8 interface.
bits : 14 - 14 (1 bit)
access : read-write
FLEXCOMM9 : Enables the clock for the Flexcomm9 interface.
bits : 15 - 15 (1 bit)
access : read-write
USB0HMR : Enables the clock for the USB host master interface.
bits : 16 - 16 (1 bit)
access : read-write
USB0HSL : Enables the clock for the USB host slave interface.
bits : 17 - 17 (1 bit)
access : read-write
SHA0 : Enables the clock for the SHA interface.
bits : 18 - 18 (1 bit)
access : read-write
SC0 : Enables the clock for the Smart card0 interface.
bits : 19 - 19 (1 bit)
access : read-write
SC1 : Enables the clock for the Smart card1 interface.
bits : 20 - 20 (1 bit)
access : read-write
Set bits in PRESETCTRLn
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_SET : Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
POR captured value of port n
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIOPORCAP : State of PIOn_31 through PIOn_0 at power-on reset
bits : 0 - 31 (32 bit)
access : read-only
Reset captured value of port n
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIORESCAP : State of PIOn_31 through PIOn_0 for resets other than POR.
bits : 0 - 31 (32 bit)
access : read-only
Clear bits in PRESETCTRLn
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_CLR : Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Main clock source select A
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Clock source for main clock source selector A
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : CLKIN
CLKIN (clk_in)
0x2 : WATCHDOG_OSCILLATOR
Watchdog oscillator (wdt_clk)
0x3 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
End of enumeration elements list.
Main clock source select B
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Clock source for main clock source selector B. Selects the clock source for the main clock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : MAINCLKSELA
MAINCLKSELA. Use the clock source selected in MAINCLKSELA register.
0x2 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x3 : RTC_OSC_OUTPUT
RTC oscillator 32 kHz output (32k_clk)
End of enumeration elements list.
CLKOUT clock source select A
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : CLKOUT clock source selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : CLKIN
CLKIN (clk_in)
0x2 : WATCHDOG_OSCILLATOR
Watchdog oscillator (wdt_clk)
0x3 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x4 : SYSTEM_PLL_OUTPUT
PLL output (pll_clk)
0x5 : USB_PLL_CLOCK
USB PLL clock (usb_pll_clk)
0x6 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x7 : RTC_OSC_OUTPUT
RTC oscillator 32 kHz output (32k_clk)
End of enumeration elements list.
PLL clock source select
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : System PLL clock source selection.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : CLKIN
CLKIN (clk_in)
0x2 : WATCHDOG_OSCILLATOR
Watchdog oscillator (wdt_clk)
0x3 : RTC_OSC_OUTPUT
RTC oscillator 32 kHz output (32k_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Audio PLL clock source select
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Audio PLL clock source selection.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : CLKIN
CLKIN (clk_in)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
SPIFI clock source select
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : System PLL clock source selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : USB_PLL_OUTPUT
USB PLL clock (usb_pll_clk)
0x3 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x4 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
ADC clock source select
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : ADC clock source selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : USB_PLL_CLOCK
USB PLL clock (usb_pll_clk)
0x3 : AUDIO_PLL_CLOCK
Audio PLL clock (audio_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
USB0 clock source select
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : USB0 device clock source selection.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : USB_PLL_CLOCK
USB PLL clock (usb_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
USB1 clock source select
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : USB1 PHY clock source selection.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : USB_PLL_CLOCK
USB PLL clock (usb_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
MCLK clock source select
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x1 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Fractional Rate Generator clock source select
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Fractional Rate Generator clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x3 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Digital microphone (DMIC) subsystem clock select
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : DMIC (audio subsystem) clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
SCTimer/PWM clock source select
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SCT clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x3 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
LCD clock source select
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : LCD clock source select.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : LCDCLKIN
LCDCLKIN (LCDCLK_EXT)
0x2 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x3 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
SDIO clock source select
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SDIO clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : MAIN_CLOCK
Main clock (main_clk)
0x1 : SYSTEM_PLL_OUTPUT
System PLL output (pll_clk)
0x2 : USB_PLL_CLOCK
USB PLL clock (usb_pll_clk)
0x3 : FRO_HF
FRO 96 or 48 MHz (fro_hf)
0x4 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
SYSTICK clock divider
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
ARM Trace clock divider
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
MCAN0 clock divider
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
MCAN1 clock divider
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
Smartcard0 clock divider
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
Smartcard1 clock divider
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
Set bits in PRESETCTRLn
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_SET : Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
AHB clock divider
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
CLKOUT clock divider
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
FROHF clock divider
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
SPIFI clock divider
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
ADC clock divider
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
USB0 clock divider
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
USB1 clock divider
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
Fractional rate divider
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional divider. MULT is equal to the programmed value.
bits : 8 - 15 (8 bit)
access : read-write
DMIC clock divider
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter. The intent is to allow the divider clock source to be changed without the risk of a glitch at the output.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
I2S MCLK clock divider
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value. 0: Divide by 1 up to 255: Divide by 256.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
LCD clock divider
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
SCT/PWM clock divider
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
EMC clock divider
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
SDIO clock divider
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : read-write
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
Clear bits in PRESETCTRLn
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_CLR : Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
System tick counter calibration
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL : System tick timer calibration value.
bits : 0 - 23 (24 bit)
access : read-write
SKEW : Initial value for the Systick timer.
bits : 24 - 24 (1 bit)
access : read-write
NOREF : Initial value for the Systick timer.
bits : 25 - 25 (1 bit)
access : read-write
Flash wait states configuration
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETCHCFG : Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NO_BUFFER
Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled.
0x1 : ONE_BUFFER
One buffer is used for all instruction fetches.
0x2 : ALL_BUFFERS
All buffers may be used for instruction fetches.
End of enumeration elements list.
DATACFG : Data read configuration. This field determines how flash accelerator buffers are used for data accesses.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NOT_BUFFERED
Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory.
0x1 : ONE_BUFFER
One buffer is used for all data accesses.
0x2 : ALL_BUFFERS
All buffers may be used for data accesses.
End of enumeration elements list.
ACCEL : Acceleration enable.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance.
0x1 : ENABLED
Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings.
End of enumeration elements list.
PREFEN : Prefetch enable.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NO_PREFETCH
No instruction prefetch is performed.
0x1 : PREFETCH
If the FETCHCFG field is not 0, the next flash line following the current execution address is automatically prefetched if it is not already buffered.
End of enumeration elements list.
PREFOVR : Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : PREFETCH_COMPLETED
Any previously initiated prefetch will be completed.
0x1 : PREFETCH_ABORT
Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered.
End of enumeration elements list.
FLASHTIM : Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1.
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : N_1_CLOCK_CYCLE
1 system clock flash access time (for system clock rates up to 12 MHz).
0x1 : N_2_CLOCK_CYCLES
2 system clocks flash access time (for system clock rates up to 30 MHz).
0x2 : N_3_CLOCK_CYCLES
3 system clocks flash access time (for system clock rates up to 60 MHz).
0x3 : N_4_CLOCK_CYCLES
4 system clocks flash access time (for system clock rates up to 85 MHz).
0x4 : N_5_CLOCK_CYCLES
5 system clocks flash access time (for system clock rates up to 100 MHz).
End of enumeration elements list.
USB0 clock control
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AP_FS_DEV_CLK : USB0 Device USB0_NEEDCLK signal control.
bits : 0 - 0 (1 bit)
access : read-write
POL_FS_DEV_CLK : USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
bits : 1 - 1 (1 bit)
access : read-write
AP_FS_HOST_CLK : USB0 Host USB0_NEEDCLK signal control.
bits : 2 - 2 (1 bit)
access : read-write
POL_FS_HOST_CLK : USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt.
bits : 3 - 3 (1 bit)
access : read-write
PU_DISABLE : Internal pull-up disable control.
bits : 4 - 4 (1 bit)
access : read-write
USB0 clock status
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_NEED_CLKST : USB0 Device USB0_NEEDCLK signal status.
bits : 0 - 0 (1 bit)
access : read-write
HOST_NEED_CLKST : USB0 Host USB0_NEEDCLK signal status.
bits : 1 - 1 (1 bit)
access : read-write
Frequency measure register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPVAL : Stores the capture result which is used to calculate the frequency of the target clock. This field is read-only.
bits : 0 - 13 (14 bit)
access : read-write
PROG : Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 13:0).
bits : 31 - 31 (1 bit)
access : read-write
MCLK input/output control
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : MCLK direction control.
bits : 0 - 0 (1 bit)
access : read-write
USB1 clock control
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AP_FS_DEV_CLK : USB1 Device need_clock signal control.
bits : 0 - 0 (1 bit)
access : read-write
POL_FS_DEV_CLK : USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt.
bits : 1 - 1 (1 bit)
access : read-write
AP_FS_HOST_CLK : USB1 Host need_clock signal control.
bits : 2 - 2 (1 bit)
access : read-write
POL_FS_HOST_CLK : USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt.
bits : 3 - 3 (1 bit)
access : read-write
HS_DEV_WAKEUP_N : External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic.
bits : 4 - 4 (1 bit)
access : read-write
USB1 clock status
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_NEED_CLKST : USB1 Device USB1_NEEDCLK signal status.
bits : 0 - 0 (1 bit)
access : read-write
HOST_NEED_CLKST : USB1 Device host USB1_NEEDCLK signal status.
bits : 1 - 1 (1 bit)
access : read-write
Set bits in AHBCLKCTRLn
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_SET : Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
EMC system control
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMCSC : EMC Shift Control.
bits : 0 - 0 (1 bit)
access : read-write
EMCRD : EMC Reset Disable.
bits : 1 - 1 (1 bit)
access : read-write
EMCBC : External Memory Controller burst control.
bits : 2 - 2 (1 bit)
access : read-write
EMCFBCLKINSEL : External Memory Controller clock select.
bits : 3 - 3 (1 bit)
access : read-write
EMC clock delay control
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_DELAY : Programmable delay value for EMC outputs in command delayed mode.
bits : 0 - 4 (5 bit)
access : read-write
FBCLK_DELAY : Programmable delay value for the feedback clock that controls input data sampling.
bits : 8 - 12 (5 bit)
access : read-write
EMC delay chain calibration control
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALVALUE : Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the FRO 12 MHz.
bits : 0 - 7 (8 bit)
access : read-write
START : Start control bit for the EMC calibration counter.
bits : 14 - 14 (1 bit)
access : read-write
DONE : Measurement completion flag.
bits : 15 - 15 (1 bit)
access : read-write
Ethernet PHY Selection
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_SEL : PHY interface select.
bits : 2 - 2 (1 bit)
access : read-write
Ethernet SBD flow control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBD_CTRL : Sideband Flow Control.
bits : 0 - 1 (2 bit)
access : read-write
SDIO CCLKIN phase and delay control
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCLK_DRV_PHASE : Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
bits : 0 - 1 (2 bit)
access : read-write
CCLK_SAMPLE_PHASE : Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
bits : 2 - 3 (2 bit)
access : read-write
PHASE_ACTIVE : sdio_clk by 2, before feeding into ccl_in, cclk_in_sample, and cclk_in_drv.
bits : 7 - 7 (1 bit)
access : read-write
CCLK_DRV_DELAY : Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
bits : 16 - 20 (5 bit)
access : read-write
CCLK_DRV_DELAY_ACTIVE : Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
bits : 23 - 23 (1 bit)
access : read-write
CCLK_SAMPLE_DELAY : Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
bits : 24 - 28 (5 bit)
access : read-write
CCLK_SAMPLE_DELAY_ACTIVE : Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
bits : 31 - 31 (1 bit)
access : read-write
NMI Source Select
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQM4 : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the Cortex-M4, if enabled by NMIENM4.
bits : 0 - 5 (6 bit)
access : read-write
NMIENM4 : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQM4.
bits : 31 - 31 (1 bit)
access : read-write
Clear bits in AHBCLKCTRLn
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_CLR : Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Set bits in PRESETCTRLn
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_SET : Writing ones to this register sets the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Asynchronous APB Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables the asynchronous APB bridge and subsystem.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. Asynchronous APB bridge is disabled.
0x1 : ENABLED
Enabled. Asynchronous APB bridge is enabled.
End of enumeration elements list.
FRO oscillator control
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : This value is factory trimmed to account for bias and temperature compensation.
bits : 0 - 13 (14 bit)
access : read-write
SEL : Select the FRO HF output frequency.
bits : 14 - 14 (1 bit)
access : read-write
FREQTRIM : Frequency trim.
bits : 16 - 23 (8 bit)
access : read-write
USBCLKADJ : USB clock adjust mode.
bits : 24 - 24 (1 bit)
access : read-write
USBMODCHG : USB Mode value Change flag.
bits : 25 - 25 (1 bit)
access : read-write
HSPDCLK : High speed clock enable.
bits : 30 - 30 (1 bit)
access : read-write
WRTRIM : Write Trim value.
bits : 31 - 31 (1 bit)
access : read-write
System oscillator control
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS : Bypass system oscillator.
bits : 0 - 0 (1 bit)
access : read-write
FREQRANGE : Determines frequency range for system oscillator.
bits : 1 - 1 (1 bit)
access : read-write
Watchdog oscillator control
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVSEL : Divider select.
bits : 0 - 4 (5 bit)
access : read-write
FREQSEL : Frequency select.
bits : 5 - 9 (5 bit)
access : read-write
Clear bits in PRESETCTRLn
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST_CLR : Writing ones to this register clears the corresponding bit or bits in the PRESETCTRLn register, if they are implemented. Bits that do not correspond to defined bits in PRESETCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
RTC oscillator 32 kHz output control
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : RTC 32 kHz clock enable.
bits : 0 - 0 (1 bit)
access : read-write
USB PLL control
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSEL : PLL feedback Divider value.
bits : 0 - 7 (8 bit)
access : read-write
PSEL : PLL Divider value.
bits : 8 - 9 (2 bit)
access : read-write
NSEL : PLL feedback Divider value.
bits : 10 - 11 (2 bit)
access : read-write
DIRECT : Direct CCO clock output control.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
CCO Clock signal goes through post divider.
0x1 : ENABLED
CCO Clock signal goes directly to output(s)..
End of enumeration elements list.
BYPASS : Input clock bypass control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
CCO clock is sent to post dividers..
0x1 : ENABLED
PLL input clock is sent to post dividers..
End of enumeration elements list.
FBSEL : Feedback divider input clock control.
bits : 14 - 14 (1 bit)
access : read-write
USB PLL status
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : USBPLL lock indicator.
bits : 0 - 0 (1 bit)
access : read-write
Flexcomm 0 clock source select
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
System PLL control
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELR : Bandwidth select R value.
bits : 0 - 3 (4 bit)
access : read-write
SELI : Bandwidth select I value.
bits : 4 - 9 (6 bit)
access : read-write
SELP : Bandwidth select P value.
bits : 10 - 14 (5 bit)
access : read-write
BYPASS : PLL bypass control.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Bypass disabled. PLL CCO is sent to the PLL post-dividers.
0x1 : ENABLED
Bypass enabled. PLL input clock is sent directly to the PLL output (default).
End of enumeration elements list.
UPLIMOFF : Disable upper frequency limiter.
bits : 17 - 17 (1 bit)
access : read-write
DIRECTI : PLL0 direct input enable.
bits : 19 - 19 (1 bit)
access : read-write
DIRECTO : PLL0 direct output enable.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The PLL output divider (P divider) is used to create the PLL output.
0x1 : ENABLED
Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
End of enumeration elements list.
PLL status
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : PLL lock indicator.
bits : 0 - 0 (1 bit)
access : read-write
PLL N divider
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDEC : Decoded N-divider coefficient value.
bits : 0 - 9 (10 bit)
access : read-write
NREQ : NDEC reload request.
bits : 10 - 10 (1 bit)
access : read-write
PLL P divider
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEC : Decoded P-divider coefficient value.
bits : 0 - 6 (7 bit)
access : read-write
PREQ : .
bits : 7 - 7 (1 bit)
access : read-write
System PLL M divider
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDEC : Decoded M-divider coefficient value.
bits : 0 - 16 (17 bit)
access : read-write
MREQ : MDEC reload request.
bits : 17 - 17 (1 bit)
access : read-write
Audio PLL control
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELR : Bandwidth select R value.
bits : 0 - 3 (4 bit)
access : read-write
SELI : Bandwidth select I value.
bits : 4 - 9 (6 bit)
access : read-write
SELP : .
bits : 10 - 14 (5 bit)
access : read-write
BYPASS : PLL bypass control.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Bypass disabled. PLL CCO is sent to the PLL post-dividers.
0x1 : ENABLED
Bypass enabled. PLL input clock is sent directly to the PLL output (default).
End of enumeration elements list.
UPLIMOFF : Disable upper frequency limiter.
bits : 17 - 17 (1 bit)
access : read-write
DIRECTI : PLL direct input enable.
bits : 19 - 19 (1 bit)
access : read-write
DIRECTO : PLL direct output enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The PLL output divider (P divider) is used to create the PLL output.
0x1 : ENABLED
Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output.
End of enumeration elements list.
Audio PLL status
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : PLL lock indicator.
bits : 0 - 0 (1 bit)
access : read-write
Audio PLL N divider
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDEC : Decoded N-divider coefficient value.
bits : 0 - 9 (10 bit)
access : read-write
NREQ : NDEC reload request.
bits : 10 - 10 (1 bit)
access : read-write
Audio PLL P divider
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEC : Decoded P-divider coefficient value.
bits : 0 - 6 (7 bit)
access : read-write
PREQ : PDEC reload request.
bits : 7 - 7 (1 bit)
access : read-write
Audio PLL M divider
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDEC : Decoded M-divider coefficient value.
bits : 0 - 16 (17 bit)
access : read-write
MREQ : MDEC reload request.
bits : 17 - 17 (1 bit)
access : read-write
Audio PLL fractional divider control
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL : PLL fractional divider control word
bits : 0 - 21 (22 bit)
access : read-write
REQ : Writing 1 to REQ signal loads CTRL value into fractional wrapper modulator.
bits : 22 - 22 (1 bit)
access : read-write
SEL_EXT : Select fractional divider.
bits : 23 - 23 (1 bit)
access : read-write
Sleep configuration register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_FRO : FRO oscillator.
bits : 4 - 4 (1 bit)
access : read-write
PDEN_TS : Temp sensor.
bits : 6 - 6 (1 bit)
access : read-write
PDEN_BOD_RST : Brown-out Detect reset.
bits : 7 - 7 (1 bit)
access : read-write
PDEN_BOD_INTR : Brown-out Detect interrupt.
bits : 8 - 8 (1 bit)
access : read-write
PDEN_VD2_ANA : Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23).
bits : 9 - 9 (1 bit)
access : read-write
PDEN_ADC0 : ADC power.
bits : 10 - 10 (1 bit)
access : read-write
PDEN_SRAMX : PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
bits : 13 - 13 (1 bit)
access : read-write
PDEN_SRAM0 : PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
bits : 14 - 14 (1 bit)
access : read-write
PDEN_SRAM1_2_3 : PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
bits : 15 - 15 (1 bit)
access : read-write
PDEN_USB_RAM : PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
bits : 16 - 16 (1 bit)
access : read-write
PDEN_ROM : ROM (also enable/disable bit 27).
bits : 17 - 17 (1 bit)
access : read-write
PDEN_VDDA : Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
bits : 19 - 19 (1 bit)
access : read-write
PDEN_WDT_OSC : Watchdog oscillator.
bits : 20 - 20 (1 bit)
access : read-write
PDEN_USB0_PHY : USB0 PHY power (also enable/disable bit 28).
bits : 21 - 21 (1 bit)
access : read-write
PDEN_SYS_PLL : System PLL (PLL0) power (also enable/disable bit 26).
bits : 22 - 22 (1 bit)
access : read-write
PDEN_VREFP : VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
bits : 23 - 23 (1 bit)
access : read-write
PDEN_VD3 : Power control for all PLLs.
bits : 26 - 26 (1 bit)
access : read-write
PDEN_VD4 : Power control for all SRAMs and ROM.
bits : 27 - 27 (1 bit)
access : read-write
PDEN_VD5 : Power control both USB0 PHY and USB1 PHY.
bits : 28 - 28 (1 bit)
access : read-write
PDEN_VD6 : Power control for EEPROM.
bits : 29 - 29 (1 bit)
access : read-write
Sleep configuration register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_USB1_PHY : USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
bits : 0 - 0 (1 bit)
access : read-write
PDEN_USB1_PLL : USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 1 - 1 (1 bit)
access : read-write
PDEN_AUD_PLL : Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 2 - 2 (1 bit)
access : read-write
PDEN_SYSOSC : System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
bits : 3 - 3 (1 bit)
access : read-write
PDEN_EEPROM : EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register).
bits : 5 - 5 (1 bit)
access : read-write
PDEN_RNG : Random Number Generator Power.
bits : 7 - 7 (1 bit)
access : read-write
Power configuration register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_FRO : FRO oscillator.
bits : 4 - 4 (1 bit)
access : read-write
PDEN_TS : Temp sensor.
bits : 6 - 6 (1 bit)
access : read-write
PDEN_BOD_RST : Brown-out Detect reset.
bits : 7 - 7 (1 bit)
access : read-write
PDEN_BOD_INTR : Brown-out Detect interrupt.
bits : 8 - 8 (1 bit)
access : read-write
PDEN_VD2_ANA : Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23).
bits : 9 - 9 (1 bit)
access : read-write
PDEN_ADC0 : ADC power.
bits : 10 - 10 (1 bit)
access : read-write
PDEN_SRAMX : PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
bits : 13 - 13 (1 bit)
access : read-write
PDEN_SRAM0 : PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
bits : 14 - 14 (1 bit)
access : read-write
PDEN_SRAM1_2_3 : PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
bits : 15 - 15 (1 bit)
access : read-write
PDEN_USB_RAM : PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
bits : 16 - 16 (1 bit)
access : read-write
PDEN_ROM : ROM (also enable/disable bit 27).
bits : 17 - 17 (1 bit)
access : read-write
PDEN_VDDA : Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
bits : 19 - 19 (1 bit)
access : read-write
PDEN_WDT_OSC : Watchdog oscillator.
bits : 20 - 20 (1 bit)
access : read-write
PDEN_USB0_PHY : USB0 PHY power (also enable/disable bit 28).
bits : 21 - 21 (1 bit)
access : read-write
PDEN_SYS_PLL : System PLL (PLL0) power (also enable/disable bit 26).
bits : 22 - 22 (1 bit)
access : read-write
PDEN_VREFP : VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
bits : 23 - 23 (1 bit)
access : read-write
PDEN_VD3 : Power control for all PLLs.
bits : 26 - 26 (1 bit)
access : read-write
PDEN_VD4 : Power control for all SRAMs and ROM.
bits : 27 - 27 (1 bit)
access : read-write
PDEN_VD5 : Power control both USB0 PHY and USB1 PHY.
bits : 28 - 28 (1 bit)
access : read-write
PDEN_VD6 : Power control for EEPROM.
bits : 29 - 29 (1 bit)
access : read-write
Power configuration register
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_USB1_PHY : USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
bits : 0 - 0 (1 bit)
access : read-write
PDEN_USB1_PLL : USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 1 - 1 (1 bit)
access : read-write
PDEN_AUD_PLL : Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 2 - 2 (1 bit)
access : read-write
PDEN_SYSOSC : System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
bits : 3 - 3 (1 bit)
access : read-write
PDEN_EEPROM : EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register).
bits : 5 - 5 (1 bit)
access : read-write
PDEN_RNG : Random Number Generator Power.
bits : 7 - 7 (1 bit)
access : read-write
Power configuration set register
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_FRO : FRO oscillator.
bits : 4 - 4 (1 bit)
access : read-write
PDEN_TS : Temp sensor.
bits : 6 - 6 (1 bit)
access : read-write
PDEN_BOD_RST : Brown-out Detect reset.
bits : 7 - 7 (1 bit)
access : read-write
PDEN_BOD_INTR : Brown-out Detect interrupt.
bits : 8 - 8 (1 bit)
access : read-write
PDEN_VD2_ANA : Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23).
bits : 9 - 9 (1 bit)
access : read-write
PDEN_ADC0 : ADC power.
bits : 10 - 10 (1 bit)
access : read-write
PDEN_SRAMX : PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
bits : 13 - 13 (1 bit)
access : read-write
PDEN_SRAM0 : PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
bits : 14 - 14 (1 bit)
access : read-write
PDEN_SRAM1_2_3 : PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
bits : 15 - 15 (1 bit)
access : read-write
PDEN_USB_RAM : PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
bits : 16 - 16 (1 bit)
access : read-write
PDEN_ROM : ROM (also enable/disable bit 27).
bits : 17 - 17 (1 bit)
access : read-write
PDEN_VDDA : Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
bits : 19 - 19 (1 bit)
access : read-write
PDEN_WDT_OSC : Watchdog oscillator.
bits : 20 - 20 (1 bit)
access : read-write
PDEN_USB0_PHY : USB0 PHY power (also enable/disable bit 28).
bits : 21 - 21 (1 bit)
access : read-write
PDEN_SYS_PLL : System PLL (PLL0) power (also enable/disable bit 26).
bits : 22 - 22 (1 bit)
access : read-write
PDEN_VREFP : VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
bits : 23 - 23 (1 bit)
access : read-write
PDEN_VD3 : Power control for all PLLs.
bits : 26 - 26 (1 bit)
access : read-write
PDEN_VD4 : Power control for all SRAMs and ROM.
bits : 27 - 27 (1 bit)
access : read-write
PDEN_VD5 : Power control both USB0 PHY and USB1 PHY.
bits : 28 - 28 (1 bit)
access : read-write
PDEN_VD6 : Power control for EEPROM.
bits : 29 - 29 (1 bit)
access : read-write
Power configuration set register
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_USB1_PHY : USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
bits : 0 - 0 (1 bit)
access : read-write
PDEN_USB1_PLL : USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 1 - 1 (1 bit)
access : read-write
PDEN_AUD_PLL : Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 2 - 2 (1 bit)
access : read-write
PDEN_SYSOSC : System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
bits : 3 - 3 (1 bit)
access : read-write
PDEN_EEPROM : EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register).
bits : 5 - 5 (1 bit)
access : read-write
PDEN_RNG : Random Number Generator Power.
bits : 7 - 7 (1 bit)
access : read-write
Power configuration clear register
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_FRO : FRO oscillator.
bits : 4 - 4 (1 bit)
access : read-write
PDEN_TS : Temp sensor.
bits : 6 - 6 (1 bit)
access : read-write
PDEN_BOD_RST : Brown-out Detect reset.
bits : 7 - 7 (1 bit)
access : read-write
PDEN_BOD_INTR : Brown-out Detect interrupt.
bits : 8 - 8 (1 bit)
access : read-write
PDEN_VD2_ANA : Analog supply for System Oscillator (also enable/disable bit 3 in PDRUNCFG1 register), Temperature Sensor (also, enable/disable bit 6), ADC (also, enable/disable bits 10, 19, and 23).
bits : 9 - 9 (1 bit)
access : read-write
PDEN_ADC0 : ADC power.
bits : 10 - 10 (1 bit)
access : read-write
PDEN_SRAMX : PDEN_SRAMX controls SRAMX (also enable/disable bit 27).
bits : 13 - 13 (1 bit)
access : read-write
PDEN_SRAM0 : PDEN_SRAM0 controls SRAM0 (also enable/disable bit 27).
bits : 14 - 14 (1 bit)
access : read-write
PDEN_SRAM1_2_3 : PDEN_SRAM1_2_3 controls SRAM1, SRAM2, and SRAM3 (also enable/disable bit 27).
bits : 15 - 15 (1 bit)
access : read-write
PDEN_USB_RAM : PDEN_USB_SRAM controls USB_RAM (also enable/disable bit 27).
bits : 16 - 16 (1 bit)
access : read-write
PDEN_ROM : ROM (also enable/disable bit 27).
bits : 17 - 17 (1 bit)
access : read-write
PDEN_VDDA : Vdda to the ADC, must be enabled for the ADC to work (also enable/disable bit 9, 10, and 23).
bits : 19 - 19 (1 bit)
access : read-write
PDEN_WDT_OSC : Watchdog oscillator.
bits : 20 - 20 (1 bit)
access : read-write
PDEN_USB0_PHY : USB0 PHY power (also enable/disable bit 28).
bits : 21 - 21 (1 bit)
access : read-write
PDEN_SYS_PLL : System PLL (PLL0) power (also enable/disable bit 26).
bits : 22 - 22 (1 bit)
access : read-write
PDEN_VREFP : VREFP to the ADC must be enabled for the ADC to work (also enable/disable bit 9, 10, and 19).
bits : 23 - 23 (1 bit)
access : read-write
PDEN_VD3 : Power control for all PLLs.
bits : 26 - 26 (1 bit)
access : read-write
PDEN_VD4 : Power control for all SRAMs and ROM.
bits : 27 - 27 (1 bit)
access : read-write
PDEN_VD5 : Power control both USB0 PHY and USB1 PHY.
bits : 28 - 28 (1 bit)
access : read-write
PDEN_VD6 : Power control for EEPROM.
bits : 29 - 29 (1 bit)
access : read-write
Power configuration clear register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_USB1_PHY : USB1 high speed PHY (also, enable/disable bit 28 in PDRUNCFG0 register).
bits : 0 - 0 (1 bit)
access : read-write
PDEN_USB1_PLL : USB PLL (PLL1) power (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 1 - 1 (1 bit)
access : read-write
PDEN_AUD_PLL : Audio PLL (PLL2) power and fractional divider (also, enable/disable bit 26 in PDRUNCFG0 register).
bits : 2 - 2 (1 bit)
access : read-write
PDEN_SYSOSC : System Oscillator Power (also, enable/disable bit 9 in PDRUNCFG0 register).
bits : 3 - 3 (1 bit)
access : read-write
PDEN_EEPROM : EEPROM power (also, enable/disable bit 29 in PDRUNCFG0 register).
bits : 5 - 5 (1 bit)
access : read-write
PDEN_RNG : Random Number Generator Power.
bits : 7 - 7 (1 bit)
access : read-write
Set bits in AHBCLKCTRLn
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_SET : Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Start logic 0 wake-up enable register
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_BOD : WWDT and BOD interrupt wake-up.
bits : 0 - 0 (1 bit)
access : read-write
DMA : DMA wake-up.
bits : 1 - 1 (1 bit)
access : read-write
GINT0 : Group interrupt 0 wake-up.
bits : 2 - 2 (1 bit)
access : read-write
GINT1 : Group interrupt 1 wake-up.
bits : 3 - 3 (1 bit)
access : read-write
PIN_INT0 : GPIO pin interrupt 0 wake-up.
bits : 4 - 4 (1 bit)
access : read-write
PIN_INT1 : GPIO pin interrupt 1 wake-up.
bits : 5 - 5 (1 bit)
access : read-write
PIN_INT2 : GPIO pin interrupt 2 wake-up.
bits : 6 - 6 (1 bit)
access : read-write
PIN_INT3 : GPIO pin interrupt 3 wake-up.
bits : 7 - 7 (1 bit)
access : read-write
UTICK : Micro-tick Timer wake-up.
bits : 8 - 8 (1 bit)
access : read-write
MRT : Multi-Rate Timer wake-up.
bits : 9 - 9 (1 bit)
access : read-write
CTIMER0 : Standard counter/timer CTIMER0 wake-up.
bits : 10 - 10 (1 bit)
access : read-write
CTIMER1 : Standard counter/timer CTIMER1 wake-up.
bits : 11 - 11 (1 bit)
access : read-write
SCT0 : SCT0 wake-up.
bits : 12 - 12 (1 bit)
access : read-write
CTIMER3 : Standard counter/timer CTIMER3 wake-up.
bits : 13 - 13 (1 bit)
access : read-write
FLEXCOMM0 : Flexcomm0 peripheral interrupt wake-up.
bits : 14 - 14 (1 bit)
access : read-write
FLEXCOMM1 : Flexcomm1 peripheral interrupt wake-up.
bits : 15 - 15 (1 bit)
access : read-write
FLEXCOMM2 : Flexcomm2 peripheral interrupt wake-up.
bits : 16 - 16 (1 bit)
access : read-write
FLEXCOMM3 : Flexcomm3 peripheral interrupt wake-up.
bits : 17 - 17 (1 bit)
access : read-write
FLEXCOMM4 : Flexcomm4 peripheral interrupt wake-up.
bits : 18 - 18 (1 bit)
access : read-write
FLEXCOMM5 : Flexcomm5 peripheral interrupt wake-up.
bits : 19 - 19 (1 bit)
access : read-write
FLEXCOMM6 : Flexcomm6 peripheral interrupt wake-up.
bits : 20 - 20 (1 bit)
access : read-write
FLEXCOMM7 : Flexcomm7 peripheral interrupt wake-up.
bits : 21 - 21 (1 bit)
access : read-write
ADC0_SEQA : ADC0 sequence A interrupt wake-up.
bits : 22 - 22 (1 bit)
access : read-write
ADC0_SEQB : ADC0 sequence B interrupt wake-up.
bits : 23 - 23 (1 bit)
access : read-write
ADC0_THCMP : ADC0 threshold and error interrupt wake-up.
bits : 24 - 24 (1 bit)
access : read-write
DMIC : Digital microphone interrupt wake-up.
bits : 25 - 25 (1 bit)
access : read-write
HWVAD : Hardware voice activity detect interrupt wake-up.
bits : 26 - 26 (1 bit)
access : read-write
USB0_NEEDCLK : USB activity interrupt wake-up.
bits : 27 - 27 (1 bit)
access : read-write
USB0 : USB function interrupt wake-up.
bits : 28 - 28 (1 bit)
access : read-write
RTC : RTC interrupt alarm and wake-up timer.
bits : 29 - 29 (1 bit)
access : read-write
Start logic 0 wake-up enable register
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINT4 : GPIO pin interrupt 4 wake-up.
bits : 0 - 0 (1 bit)
access : read-write
PINT5 : GPIO pin interrupt 5 wake-up.
bits : 1 - 1 (1 bit)
access : read-write
PINT6 : GPIO pin interrupt 6 wake-up.
bits : 2 - 2 (1 bit)
access : read-write
PINT7 : GPIO pin interrupt 7 wake-up.
bits : 3 - 3 (1 bit)
access : read-write
CTIMER2 : Standard counter/timer CTIMER2 wake-up.
bits : 4 - 4 (1 bit)
access : read-write
CTIMER4 : Standard counter/timer CTIMER4 wake-up.
bits : 5 - 5 (1 bit)
access : read-write
SPIFI : SPIFI interrupt wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.
bits : 7 - 7 (1 bit)
access : read-write
FLEXCOMM8 : Flexcomm Interface 8 wake-up.
bits : 8 - 8 (1 bit)
access : read-write
FLEXCOMM9 : Flexcomm Interface 9 wake-up.
bits : 9 - 9 (1 bit)
access : read-write
USB1 : USB 1 wake-up.
bits : 15 - 15 (1 bit)
access : read-write
USB1_ACT : USB 1 activity wake-up.
bits : 16 - 16 (1 bit)
access : read-write
ENET_INT1 : Ethernet.
bits : 17 - 17 (1 bit)
access : read-write
ENET_INT2 : Ethernet.
bits : 18 - 18 (1 bit)
access : read-write
ENET_INT0 : Ethernet.
bits : 19 - 19 (1 bit)
access : read-write
SMARTCARD0 : Smart card 0 wake-up.
bits : 23 - 23 (1 bit)
access : read-write
SMARTCARD1 : Smart card 1 wake-up.
bits : 24 - 24 (1 bit)
access : read-write
Clear bits in AHBCLKCTRLn
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_CLR : Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Configures special cases of hardware wake-up
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEWAKE : Force peripheral clocking to stay on during Deep Sleep and Power-down modes. When 1, clocking to peripherals is prevented from being shut down when the CPU enters Deep Sleep and Power-down modes. This is intended to allow a coprocessor to continue operating while the main CPU(s) are shut down.
bits : 0 - 0 (1 bit)
access : read-write
FCWAKE : Wake for Flexcomms. When 1, any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted.
bits : 1 - 1 (1 bit)
access : read-write
WAKEDMIC : Wake for Digital Microphone. When 1, the digital microphone input FIFO reaching the level specified by TRIGLVL of either channel will cause peripheral clocking to wake up temporarily while the related status is asserted.
bits : 2 - 2 (1 bit)
access : read-write
WAKEDMA : Wake for DMA. When 1, DMA being busy will cause peripheral clocking to remain running until DMA completes. This is generally used in conjunction with bit 1 and/or 2 in order to prevent peripheral clocking from being shut down as soon as the cause of wake-up is cleared, but before DMA has completed its related activity.
bits : 3 - 3 (1 bit)
access : read-write
Flexcomm 0 clock source select
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Set bits in AHBCLKCTRLn
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_SET : Writing ones to this register sets the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Clear bits in AHBCLKCTRLn
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLK_CLR : Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRLn register, if they are implemented. Bits that do not correspond to defined bits in AHBCLKCTRLn are reserved and only zeroes should be written to them.
bits : 0 - 31 (32 bit)
access : write-only
Flexcomm 0 clock source select
address_offset : 0xACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Set bits in STARTER
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START_SET : Writing ones to this register sets the corresponding bit or bits in the STARTER0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
Clear bits in STARTER0
address_offset : 0xD80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START_CLR : Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
Flexcomm 0 clock source select
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Flexcomm clock source selection. One per Flexcomm.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : FRO_12_MHZ
FRO 12 MHz (fro_12m)
0x1 : FRO_HF_DIV
FRO HF DIV (fro_hf_div)
0x2 : AUDIO_PLL_OUTPUT
Audio PLL clock (audio_pll_clk)
0x3 : MCLK_INPUT
MCLK pin input, when selected in IOCON (mclk_in)
0x4 : FRG_CLOCK_OUTPUT
FRG clock, the output of the fractional rate generator (frg_clk)
0x7 : NONE
None, this may be selected in order to reduce power when no output is needed.
End of enumeration elements list.
Auto Clock-Gate Override Register
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM0X : When 1, automatic clock gating for RAMX and RAM0 are turned off.
bits : 1 - 1 (1 bit)
access : read-write
RAM1 : When 1, automatic clock gating for RAM1 are turned off.
bits : 2 - 2 (1 bit)
access : read-write
RAM2 : When 1, automatic clock gating for RAM1 are turned off.
bits : 3 - 3 (1 bit)
access : read-write
RAM3 : When 1, automatic clock gating for RAM1 are turned off.
bits : 4 - 4 (1 bit)
access : read-write
JTAG ID code register
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JTAGID : JTAG ID code.
bits : 0 - 31 (32 bit)
access : read-only
Part ID register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTID : Part ID
bits : 0 - 31 (32 bit)
access : read-only
Boot ROM and die revision register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVID : Revision.
bits : 0 - 31 (32 bit)
access : read-only
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