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UTICK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CAP[0]

CAP[1]

STAT

CAP[2]

CAP[3]

CFG

CAPCLR


CTRL

Control register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELAYVAL REPEAT

DELAYVAL : Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
bits : 0 - 30 (31 bit)
access : read-write

REPEAT : Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
bits : 31 - 31 (1 bit)
access : read-write


CAP[0]

Capture register .
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP[0] CAP[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_VALUE VALID

CAP_VALUE : Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event.
bits : 0 - 30 (31 bit)
access : read-only

VALID : Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
bits : 31 - 31 (1 bit)
access : read-only


CAP[1]

Capture register .
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP[1] CAP[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_VALUE VALID

CAP_VALUE : Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event.
bits : 0 - 30 (31 bit)
access : read-only

VALID : Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
bits : 31 - 31 (1 bit)
access : read-only


STAT

Status register.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTR ACTIVE

INTR : Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any value to this register clears this flag.
bits : 0 - 0 (1 bit)
access : read-write

ACTIVE : Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
bits : 1 - 1 (1 bit)
access : read-write


CAP[2]

Capture register .
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP[2] CAP[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_VALUE VALID

CAP_VALUE : Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event.
bits : 0 - 30 (31 bit)
access : read-only

VALID : Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
bits : 31 - 31 (1 bit)
access : read-only


CAP[3]

Capture register .
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAP[3] CAP[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAP_VALUE VALID

CAP_VALUE : Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event.
bits : 0 - 30 (31 bit)
access : read-only

VALID : Capture Valid. When 1, a value has been captured based on a transition of the related UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
bits : 31 - 31 (1 bit)
access : read-only


CFG

Capture configuration register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPEN0 CAPEN1 CAPEN2 CAPEN3 CAPPOL0 CAPPOL1 CAPPOL2 CAPPOL3

CAPEN0 : Enable Capture 0. 1 = Enabled, 0 = Disabled.
bits : 0 - 0 (1 bit)
access : read-write

CAPEN1 : Enable Capture 1. 1 = Enabled, 0 = Disabled.
bits : 1 - 1 (1 bit)
access : read-write

CAPEN2 : Enable Capture 2. 1 = Enabled, 0 = Disabled.
bits : 2 - 2 (1 bit)
access : read-write

CAPEN3 : Enable Capture 3. 1 = Enabled, 0 = Disabled.
bits : 3 - 3 (1 bit)
access : read-write

CAPPOL0 : Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
bits : 8 - 8 (1 bit)
access : read-write

CAPPOL1 : Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
bits : 9 - 9 (1 bit)
access : read-write

CAPPOL2 : Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
bits : 10 - 10 (1 bit)
access : read-write

CAPPOL3 : Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
bits : 11 - 11 (1 bit)
access : read-write


CAPCLR

Capture clear register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CAPCLR CAPCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPCLR0 CAPCLR1 CAPCLR2 CAPCLR3

CAPCLR0 : Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
bits : 0 - 0 (1 bit)
access : write-only

CAPCLR1 : Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
bits : 1 - 1 (1 bit)
access : write-only

CAPCLR2 : Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
bits : 2 - 2 (1 bit)
access : write-only

CAPCLR3 : Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
bits : 3 - 3 (1 bit)
access : write-only



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