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address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONTROLLER_RESET : Controller reset.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_RESET : Fifo reset.
bits : 1 - 1 (1 bit)
access : read-write
DMA_RESET : DMA reset.
bits : 2 - 2 (1 bit)
access : read-write
INT_ENABLE : Global interrupt enable/disable bit.
bits : 4 - 4 (1 bit)
access : read-write
READ_WAIT : Read/wait.
bits : 6 - 6 (1 bit)
access : read-write
SEND_IRQ_RESPONSE : Send irq response.
bits : 7 - 7 (1 bit)
access : read-write
ABORT_READ_DATA : Abort read data.
bits : 8 - 8 (1 bit)
access : read-write
SEND_CCSD : Send ccsd.
bits : 9 - 9 (1 bit)
access : read-write
SEND_AUTO_STOP_CCSD : Send auto stop ccsd.
bits : 10 - 10 (1 bit)
access : read-write
CEATA_DEVICE_INTERRUPT_STATUS : CEATA device interrupt status.
bits : 11 - 11 (1 bit)
access : read-write
CARD_VOLTAGE_A0 : Controls the state of the SD_VOLT0 pin.
bits : 16 - 16 (1 bit)
access : read-write
CARD_VOLTAGE_A1 : Controls the state of the SD_VOLT1 pin.
bits : 17 - 17 (1 bit)
access : read-write
CARD_VOLTAGE_A2 : Controls the state of the SD_VOLT2 pin.
bits : 18 - 18 (1 bit)
access : read-write
USE_INTERNAL_DMAC : SD/MMC DMA use.
bits : 25 - 25 (1 bit)
access : read-write
Clock Enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCLK_ENABLE : Clock-enable control for SD card clock.
bits : 0 - 0 (1 bit)
access : read-write
CCLK_LOW_POWER : Low-power control for SD card clock.
bits : 16 - 16 (1 bit)
access : read-write
Card Threshold Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARDRDTHREN : Card Read Threshold Enable.
bits : 0 - 0 (1 bit)
access : read-write
BSYCLRINTEN : Busy Clear Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-write
CARDTHRESHOLD : Card Threshold size.
bits : 16 - 23 (8 bit)
access : read-write
Power control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BACKENDPWR : Back-end Power control for card application.
bits : 0 - 0 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Response register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Time-out register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPONSE_TIMEOUT : Response time-out value.
bits : 0 - 7 (8 bit)
access : read-write
DATA_TIMEOUT : Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
bits : 8 - 31 (24 bit)
access : read-write
SDIF FIFO
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Card Type register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARD_WIDTH0 : Indicates if card is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0).
bits : 0 - 0 (1 bit)
access : read-write
CARD_WIDTH1 : Indicates if card is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
bits : 16 - 16 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Block Size register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCK_SIZE : Block size.
bits : 0 - 15 (16 bit)
access : read-write
SDIF FIFO
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Byte Count register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTE_COUNT : Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write
RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write
CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write
DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write
TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write
RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write
RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write
DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write
RTO : Response time-out.
bits : 8 - 8 (1 bit)
access : read-write
DRTO : Data read time-out.
bits : 9 - 9 (1 bit)
access : read-write
HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write
FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write
HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write
SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write
ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write
EBE : End-bit error (read)/Write no CRC.
bits : 15 - 15 (1 bit)
access : read-write
SDIO_INT_MASK : Mask SDIO interrupt.
bits : 16 - 16 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Command Argument register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_ARG : Value indicates command argument to be passed to card.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Command register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_INDEX : Command index.
bits : 0 - 5 (6 bit)
access : read-write
RESPONSE_EXPECT : Response expect.
bits : 6 - 6 (1 bit)
access : read-write
RESPONSE_LENGTH : Response length.
bits : 7 - 7 (1 bit)
access : read-write
CHECK_RESPONSE_CRC : Check response CRC.
bits : 8 - 8 (1 bit)
access : read-write
DATA_EXPECTED : Data expected.
bits : 9 - 9 (1 bit)
access : read-write
READ_WRITE : read/write.
bits : 10 - 10 (1 bit)
access : read-write
TRANSFER_MODE : Transfer mode.
bits : 11 - 11 (1 bit)
access : read-write
SEND_AUTO_STOP : Send auto stop.
bits : 12 - 12 (1 bit)
access : read-write
WAIT_PRVDATA_COMPLETE : Wait prvdata complete.
bits : 13 - 13 (1 bit)
access : read-write
STOP_ABORT_CMD : Stop abort command.
bits : 14 - 14 (1 bit)
access : read-write
SEND_INITIALIZATION : Send initialization.
bits : 15 - 15 (1 bit)
access : read-write
UPDATE_CLOCK_REGISTERS_ONLY : Update clock registers only.
bits : 21 - 21 (1 bit)
access : read-write
READ_CEATA_DEVICE : Read ceata device.
bits : 22 - 22 (1 bit)
access : read-write
CCS_EXPECTED : CCS expected.
bits : 23 - 23 (1 bit)
access : read-write
ENABLE_BOOT : Enable Boot - this bit should be set only for mandatory boot mode.
bits : 24 - 24 (1 bit)
access : read-write
EXPECT_BOOT_ACK : Expect Boot Acknowledge.
bits : 25 - 25 (1 bit)
access : read-write
DISABLE_BOOT : Disable Boot.
bits : 26 - 26 (1 bit)
access : read-write
BOOT_MODE : Boot Mode.
bits : 27 - 27 (1 bit)
access : read-write
VOLT_SWITCH : Voltage switch bit.
bits : 28 - 28 (1 bit)
access : read-write
USE_HOLD_REG : Use Hold Register.
bits : 29 - 29 (1 bit)
access : read-write
START_CMD : Start command.
bits : 31 - 31 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Power Enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWER_ENABLE : Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.
bits : 0 - 0 (1 bit)
access : read-write
Masked Interrupt Status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write
RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write
CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write
DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write
TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write
RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write
RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write
DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write
RTO : Response time-out.
bits : 8 - 8 (1 bit)
access : read-write
DRTO : Data read time-out.
bits : 9 - 9 (1 bit)
access : read-write
HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write
FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write
HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write
SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write
ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write
EBE : End-bit error (read)/write no CRC.
bits : 15 - 15 (1 bit)
access : read-write
SDIO_INTERRUPT : Interrupt from SDIO card.
bits : 16 - 16 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Raw Interrupt Status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write
RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write
CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write
DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write
TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write
RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write
RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write
DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write
RTO_BAR : Response time-out (RTO)/Boot Ack Received (BAR).
bits : 8 - 8 (1 bit)
access : read-write
DRTO_BDS : Data read time-out (DRTO)/Boot Data Start (BDS).
bits : 9 - 9 (1 bit)
access : read-write
HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write
FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write
HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write
SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write
ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write
EBE : End-bit error (read)/write no CRC.
bits : 15 - 15 (1 bit)
access : read-write
SDIO_INTERRUPT : Interrupt from SDIO card.
bits : 16 - 16 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFO_RX_WATERMARK : FIFO reached Receive watermark level; not qualified with data transfer.
bits : 0 - 0 (1 bit)
access : read-write
FIFO_TX_WATERMARK : FIFO reached Transmit watermark level; not qualified with data transfer.
bits : 1 - 1 (1 bit)
access : read-write
FIFO_EMPTY : FIFO is empty status.
bits : 2 - 2 (1 bit)
access : read-write
FIFO_FULL : FIFO is full status.
bits : 3 - 3 (1 bit)
access : read-write
CMDFSMSTATES : Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits.
bits : 4 - 7 (4 bit)
access : read-write
DATA_3_STATUS : Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
bits : 8 - 8 (1 bit)
access : read-write
DATA_BUSY : Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
bits : 9 - 9 (1 bit)
access : read-write
DATA_STATE_MC_BUSY : Data transmit or receive state-machine is busy.
bits : 10 - 10 (1 bit)
access : read-write
RESPONSE_INDEX : Index of previous response, including any auto-stop sent by core.
bits : 11 - 16 (6 bit)
access : read-write
FIFO_COUNT : FIFO count - Number of filled locations in FIFO.
bits : 17 - 29 (13 bit)
access : read-write
DMA_ACK : DMA acknowledge signal state.
bits : 30 - 30 (1 bit)
access : read-write
DMA_REQ : DMA request signal state.
bits : 31 - 31 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
FIFO Threshold Watermark register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_WMARK : FIFO threshold watermark level when transmitting data to card.
bits : 0 - 11 (12 bit)
access : read-write
RX_WMARK : FIFO threshold watermark level when receiving data to card.
bits : 16 - 27 (12 bit)
access : read-write
DMA_MTS : Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.
bits : 28 - 30 (3 bit)
access : read-write
SDIF FIFO
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Card Detect register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARD_DETECT : Card detect.
bits : 0 - 0 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Write Protect register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRITE_PROTECT : Write protect.
bits : 0 - 0 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Transferred CIU Card Byte Count register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANS_CARD_BYTE_COUNT : Number of bytes transferred by CIU unit to card.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Response register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write
Transferred Host to BIU-FIFO Byte Count register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANS_FIFO_BYTE_COUNT : Number of bytes transferred between Host/DMA memory and BIU FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Debounce Count register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBOUNCE_COUNT : Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
bits : 0 - 23 (24 bit)
access : read-write
SDIF FIFO
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x7660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Hardware Reset
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CARD_RESET : Hardware reset.
bits : 0 - 0 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x7924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x7BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x7EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Clock Divider register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_DIVIDER0 : Clock divider-0 value.
bits : 0 - 7 (8 bit)
access : read-write
Bus Mode register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset.
bits : 0 - 0 (1 bit)
access : read-write
FB : Fixed Burst.
bits : 1 - 1 (1 bit)
access : read-write
DSL : Descriptor Skip Length.
bits : 2 - 6 (5 bit)
access : read-write
DE : SD/MMC DMA Enable.
bits : 7 - 7 (1 bit)
access : read-write
PBL : Programmable Burst Length.
bits : 8 - 10 (3 bit)
access : read-write
SDIF FIFO
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Poll Demand register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : Poll Demand.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x8734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor List Base Address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDL : Start of Descriptor List.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Internal DMAC Status register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI : Transmit Interrupt.
bits : 0 - 0 (1 bit)
access : read-write
RI : Receive Interrupt.
bits : 1 - 1 (1 bit)
access : read-write
FBE : Fatal Bus Error Interrupt.
bits : 2 - 2 (1 bit)
access : read-write
DU : Descriptor Unavailable Interrupt.
bits : 4 - 4 (1 bit)
access : read-write
CES : Card Error Summary.
bits : 5 - 5 (1 bit)
access : read-write
NIS : Normal Interrupt Summary.
bits : 8 - 8 (1 bit)
access : read-write
AIS : Abnormal Interrupt Summary.
bits : 9 - 9 (1 bit)
access : read-write
EB : Error Bits.
bits : 10 - 12 (3 bit)
access : read-write
FSM : DMAC state machine present state.
bits : 13 - 16 (4 bit)
access : read-write
SDIF FIFO
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x8FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Internal DMAC Interrupt Enable register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI : Transmit Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write
RI : Receive Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-write
FBE : Fatal Bus Error Enable.
bits : 2 - 2 (1 bit)
access : read-write
DU : Descriptor Unavailable Interrupt.
bits : 4 - 4 (1 bit)
access : read-write
CES : Card Error summary Interrupt Enable.
bits : 5 - 5 (1 bit)
access : read-write
NIS : Normal Interrupt Summary Enable.
bits : 8 - 8 (1 bit)
access : read-write
AIS : Abnormal Interrupt Summary Enable.
bits : 9 - 9 (1 bit)
access : read-write
SDIF FIFO
address_offset : 0x92BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Response register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write
Current Host Descriptor Address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDA : Host Descriptor Address Pointer.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x95A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Current Buffer Descriptor Address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HBA : Host Buffer Address Pointer.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x9B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0x9E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
Response register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write
SDIF FIFO
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write
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