\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
GPIO grouped interrupt control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
No request. No interrupt request is pending.
0x1 : REQUEST_ACTIVE
Request active. Interrupt request is active.
End of enumeration elements list.
COMB : Combine enabled inputs for group interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : OR
Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
0x1 : AND
And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
End of enumeration elements list.
TRIG : Group interrupt trigger
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EDGE_TRIGGERED
Edge-triggered.
0x1 : LEVEL_TRIGGERED
Level-triggered.
End of enumeration elements list.
GPIO grouped interrupt port 0 polarity register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL : Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
bits : 0 - 31 (32 bit)
access : read-write
GPIO grouped interrupt port 0 polarity register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL : Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
bits : 0 - 31 (32 bit)
access : read-write
GPIO grouped interrupt port 0 enable register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENA : Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
bits : 0 - 31 (32 bit)
access : read-write
GPIO grouped interrupt port 0 enable register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENA : Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
bits : 0 - 31 (32 bit)
access : read-write
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