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address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected
This register contains the offset value towards the start of the operational register space and the version number of the IP block
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPLENGTH : Capability Length: This is used as an offset.
bits : 0 - 7 (8 bit)
access : read-only
CHIPID : Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
bits : 16 - 31 (16 bit)
access : read-only
Memory base address where ATL PTD0 is stored
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATL_CUR : This indicates the current PTD that is used by the hardware when it is processing the ATL list.
bits : 4 - 8 (5 bit)
access : read-write
ATL_BASE : Base address to be used by the hardware to find the start of the ATL list.
bits : 9 - 31 (23 bit)
access : read-write
Memory base address where ISO PTD0 is stored
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISO_FIRST : This indicates the first PTD that is used by the hardware when it is processing the ISO list.
bits : 5 - 9 (5 bit)
access : read-write
ISO_BASE : Base address to be used by the hardware to find the start of the ISO list.
bits : 10 - 31 (22 bit)
access : read-write
Memory base address where INT PTD0 is stored
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_FIRST : This indicates the first PTD that is used by the hardware when it is processing the INT list.
bits : 5 - 9 (5 bit)
access : read-write
INT_BASE : Base address to be used by the hardware to find the start of the INT list.
bits : 10 - 31 (22 bit)
access : read-write
Memory base address that indicates the start of the data payload buffers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT_BASE : Base address to be used by the hardware to find the start of the data payload section.
bits : 16 - 31 (16 bit)
access : read-write
USB Command register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RS : Run/Stop: 1b = Run.
bits : 0 - 0 (1 bit)
access : read-write
HCRESET : Host Controller Reset: This control bit is used by the software to reset the host controller.
bits : 1 - 1 (1 bit)
access : read-write
FLS : Frame List Size: This field specifies the size of the frame list.
bits : 2 - 3 (2 bit)
access : read-write
LHCR : Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports.
bits : 7 - 7 (1 bit)
access : read-write
ATL_EN : ATL List enabled.
bits : 8 - 8 (1 bit)
access : read-write
ISO_EN : ISO List enabled.
bits : 9 - 9 (1 bit)
access : read-write
INT_EN : INT List enabled.
bits : 10 - 10 (1 bit)
access : read-write
HIRD : Host-Initiated Resume Duration.
bits : 24 - 27 (4 bit)
access : read-write
USB Interrupt Status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port.
bits : 2 - 2 (1 bit)
access : read-write
FLR : Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0.
bits : 3 - 3 (1 bit)
access : read-write
ATL_IRQ : ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
bits : 16 - 16 (1 bit)
access : read-write
ISO_IRQ : ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
bits : 17 - 17 (1 bit)
access : read-write
INT_IRQ : INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
bits : 18 - 18 (1 bit)
access : read-write
SOF_IRQ : SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
bits : 19 - 19 (1 bit)
access : read-write
USB Interrupt Enable register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCDE : Port Change Detect Interrupt Enable: 1: enable 0: disable.
bits : 2 - 2 (1 bit)
access : read-write
FLRE : Frame List Rollover Interrupt Enable: 1: enable 0: disable.
bits : 3 - 3 (1 bit)
access : read-write
ATL_IRQ_E : ATL IRQ Enable bit: 1: enable 0: disable.
bits : 16 - 16 (1 bit)
access : read-write
ISO_IRQ_E : ISO IRQ Enable bit: 1: enable 0: disable.
bits : 17 - 17 (1 bit)
access : read-write
INT_IRQ_E : INT IRQ Enable bit: 1: enable 0: disable.
bits : 18 - 18 (1 bit)
access : read-write
SOF_E : SOF Interrupt Enable bit: 1: enable 0: disable.
bits : 19 - 19 (1 bit)
access : read-write
Port Status and Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCS : Current Connect Status: Logic 1 indicates a device is present on the port.
bits : 0 - 0 (1 bit)
access : read-write
CSC : Connect Status Change: Logic 1 means that the value of CCS has changed.
bits : 1 - 1 (1 bit)
access : read-write
PED : Port Enabled/Disabled.
bits : 2 - 2 (1 bit)
access : read-write
PEDC : Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
bits : 3 - 3 (1 bit)
access : read-write
OCA : Over-current active: Logic 1 means that this port has an over-current condition.
bits : 4 - 4 (1 bit)
access : read-write
OCC : Over-current change: Logic 1 means that the value of OCA has changed.
bits : 5 - 5 (1 bit)
access : read-write
FPR : Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
bits : 6 - 6 (1 bit)
access : read-write
SUSP : Suspend: Logic 1 means port is in the suspend state.
bits : 7 - 7 (1 bit)
access : read-write
PR : Port Reset: Logic 1 means the port is in the reset state.
bits : 8 - 8 (1 bit)
access : read-write
SUS_L1 : Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume.
bits : 9 - 9 (1 bit)
access : read-write
LS : Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
bits : 10 - 11 (2 bit)
access : read-only
PP : Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
bits : 12 - 12 (1 bit)
access : read-write
PIC : Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0.
bits : 14 - 15 (2 bit)
access : read-write
PTC : Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
bits : 16 - 19 (4 bit)
access : read-write
PSPD : Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
bits : 20 - 21 (2 bit)
access : read-write
WOO : Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events.
bits : 22 - 22 (1 bit)
access : read-write
SUS_STAT : These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred.
bits : 23 - 24 (2 bit)
access : read-write
DEV_ADD : Device Address for LPM tokens.
bits : 25 - 31 (7 bit)
access : read-write
Done map for each ATL PTD
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATL_DONE : The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
bits : 0 - 31 (32 bit)
access : read-write
Skip map for each ATL PTD
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATL_SKIP : When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting.
bits : 0 - 31 (32 bit)
access : read-write
Done map for each ISO PTD
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISO_DONE : The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
bits : 0 - 31 (32 bit)
access : read-write
Skip map for each ISO PTD
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISO_SKIP : The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
bits : 0 - 31 (32 bit)
access : read-write
Host Controller Structural Parameters
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
N_PORTS : This register specifies the number of physical downstream ports implemented on this host controller.
bits : 0 - 3 (4 bit)
access : read-only
PPC : This field indicates whether the host controller implementation includes port power control.
bits : 4 - 4 (1 bit)
access : read-only
P_INDICATOR : This bit indicates whether the ports support port indicator control.
bits : 16 - 16 (1 bit)
access : read-only
Done map for each INT PTD
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_DONE : The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
bits : 0 - 31 (32 bit)
access : read-write
Skip map for each INT PTD
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_SKIP : When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be skipped, independent of the V bit setting.
bits : 0 - 31 (32 bit)
access : read-write
Marks the last PTD in the list for ISO, INT and ATL
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATL_LAST : If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
bits : 0 - 4 (5 bit)
access : read-write
ISO_LAST : This indicates the last PTD in the ISO list.
bits : 8 - 12 (5 bit)
access : read-write
INT_LAST : This indicates the last PTD in the INT list.
bits : 16 - 20 (5 bit)
access : read-write
Controls the port if it is attached to the host block or the device block
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID0 : Port 0 ID pin value.
bits : 0 - 0 (1 bit)
access : read-write
ID0_EN : Port 0 ID pin pull-up enable.
bits : 8 - 8 (1 bit)
access : read-write
DEV_ENABLE : If this bit is set to one, one of the ports will behave as a USB device.
bits : 16 - 16 (1 bit)
access : read-write
SW_CTRL_PDCOM : This bit indicates if the PHY power-down input is controlled by software or by hardware.
bits : 18 - 18 (1 bit)
access : read-write
SW_PDCOM : This bit is only used when SW_CTRL_PDCOM is set to 1b.
bits : 19 - 19 (1 bit)
access : read-write
Host Controller Capability Parameters
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPMC : Link Power Management Capability.
bits : 17 - 17 (1 bit)
access : read-only
Frame Length Adjustment
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLADJ : Frame Length Timing Value.
bits : 0 - 5 (6 bit)
access : read-write
FRINDEX : Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
bits : 16 - 29 (14 bit)
access : read-write
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