\n

GINT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

PORT_POL[0]

PORT_POL[1]

PORT_ENA[0]

PORT_ENA[1]


CTRL

GPIO grouped interrupt control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT COMB TRIG

INT : Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NO_REQUEST

No request. No interrupt request is pending.

0x1 : REQUEST_ACTIVE

Request active. Interrupt request is active.

End of enumeration elements list.

COMB : Combine enabled inputs for group interrupt
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : OR

Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).

0x1 : AND

And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).

End of enumeration elements list.

TRIG : Group interrupt trigger
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : EDGE_TRIGGERED

Edge-triggered.

0x1 : LEVEL_TRIGGERED

Level-triggered.

End of enumeration elements list.


PORT_POL[0]

GPIO grouped interrupt port 0 polarity register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORT_POL[0] PORT_POL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POL

POL : Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
bits : 0 - 31 (32 bit)
access : read-write


PORT_POL[1]

GPIO grouped interrupt port 0 polarity register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORT_POL[1] PORT_POL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POL

POL : Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt.
bits : 0 - 31 (32 bit)
access : read-write


PORT_ENA[0]

GPIO grouped interrupt port 0 enable register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORT_ENA[0] PORT_ENA[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA

ENA : Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
bits : 0 - 31 (32 bit)
access : read-write


PORT_ENA[1]

GPIO grouped interrupt port 0 enable register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORT_ENA[1] PORT_ENA[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA

ENA : Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is enabled and contributes to the grouped interrupt.
bits : 0 - 31 (32 bit)
access : read-write



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