Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected
192MHz Free Running OScillator (FRO) Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENA_12MHZCLK : 12 MHz clock control.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
12 MHz clock is disabled.
0x1 : ENABLE
12 MHz clock is enabled.
End of enumeration elements list.
DAC_TRIM : Frequency trim.
bits : 16 - 23 (8 bit)
access : read-write
USBCLKADJ : If this bit is set and the USB peripheral is enabled into full speed device mode, the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets.
bits : 24 - 24 (1 bit)
access : read-write
USBMODCHG : If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
bits : 25 - 25 (1 bit)
access : read-only
ENA_96MHZCLK : 96 MHz clock control.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
96 MHz clock is disabled.
0x1 : ENABLE
96 MHz clock is enabled.
End of enumeration elements list.
192MHz Free Running OScillator (FRO) Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_VALID : Output clock valid signal. Indicates that CCO clock has settled.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOCLKOUT
No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
0x1 : CLKOUT
Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
End of enumeration elements list.
ATB_VCTRL : CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses the threshold voltage of a SLVT transistor, this output signal will go high. It is also possible to observe the clk_valid signal.
bits : 1 - 1 (1 bit)
access : read-only
High speed Crystal Oscillator Control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACBUF_PASS_ENABLE : Bypass enable of XO AC buffer enable in pll and top level.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
XO AC buffer bypass is disabled.
0x1 : ENABLE
XO AC buffer bypass is enabled.
End of enumeration elements list.
ENABLE_PLL_USB_OUT : Enable High speed Crystal oscillator output to USB HS PLL.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
High speed Crystal oscillator output to USB HS PLL is disabled.
0x1 : ENABLE
High speed Crystal oscillator output to USB HS PLL is enabled.
End of enumeration elements list.
ENABLE_SYSTEM_CLK_OUT : Enable High speed Crystal oscillator output to CPU system.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
High speed Crystal oscillator output to CPU system is disabled.
0x1 : ENABLE
High speed Crystal oscillator output to CPU system is enabled.
End of enumeration elements list.
High speed Crystal Oscillator Status register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XO_READY : Indicates XO out frequency statibilty.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_STABLE
XO output frequency is not yet stable.
0x1 : STABLE
XO output frequency is stable.
End of enumeration elements list.
Brown Out Detectors (BoDs) and DCDC interrupts generation control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODVBAT_INT_ENABLE : BOD VBAT interrupt control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
BOD VBAT interrupt is disabled.
0x1 : ENABLE
BOD VBAT interrupt is enabled.
End of enumeration elements list.
BODVBAT_INT_CLEAR : BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
bits : 1 - 1 (1 bit)
access : read-write
BODCORE_INT_ENABLE : BOD CORE interrupt control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
BOD CORE interrupt is disabled.
0x1 : ENABLE
BOD CORE interrupt is enabled.
End of enumeration elements list.
BODCORE_INT_CLEAR : BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
bits : 3 - 3 (1 bit)
access : read-write
DCDC_INT_ENABLE : DCDC interrupt control.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
DCDC interrupt is disabled.
0x1 : ENABLE
DCDC interrupt is enabled.
End of enumeration elements list.
DCDC_INT_CLEAR : DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
bits : 5 - 5 (1 bit)
access : read-write
BoDs and DCDC interrupts status register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BODVBAT_STATUS : BOD VBAT Interrupt status before Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
BODVBAT_INT_STATUS : BOD VBAT Interrupt status after Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
BODVBAT_VAL : Current value of BOD VBAT power status output.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NOT_OK
VBAT voltage level is below the threshold.
0x1 : OK
VBAT voltage level is above the threshold.
End of enumeration elements list.
BODCORE_STATUS : BOD CORE Interrupt status before Interrupt Enable.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
BODCORE_INT_STATUS : BOD CORE Interrupt status after Interrupt Enable.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
BODCORE_VAL : Current value of BOD CORE power status output.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : NOT_OK
CORE voltage level is below the threshold.
0x1 : OK
CORE voltage level is above the threshold.
End of enumeration elements list.
DCDC_STATUS : DCDC Interrupt status before Interrupt Enable.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
DCDC_INT_STATUS : DCDC Interrupt status after Interrupt Enable.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : NOT_PENDING
No interrupt pending..
0x1 : PENDING
Interrupt pending..
End of enumeration elements list.
DCDC_VAL : Current value of DCDC power status output.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : NOT_OK
DCDC output Voltage is below the targeted regulation level.
0x1 : OK
DCDC output Voltage is above the targeted regulation level.
End of enumeration elements list.
Analog Macroblock Identity registers, Flash Status registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLASH_PWRDWN : Flash Power Down status.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : PWRUP
Flash is not in power down mode.
0x1 : PWRDWN
Flash is in power down mode.
End of enumeration elements list.
FLASH_INIT_ERROR : Flash initialization error status.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : NOERROR
No error.
0x1 : ERROR
At least one error occured during flash initialization..
End of enumeration elements list.
Frequency Measure function control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPVAL_SCALE : Frequency measure result /Frequency measur scale
bits : 0 - 30 (31 bit)
access : read-write
PROG : Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit when the measurement cycle has completed and there is valid capture data in the CAPVAL field (bits 30:0).
bits : 31 - 31 (1 bit)
access : read-write
Dummy Control bus to analog modules
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XO32M_ADC_CLK_MODE : Control High speed Crystal oscillator mode of the ADC clock.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
High speed Crystal oscillator output to ADC is disabled.
0x1 : XO_ADC_ENABLE
High speed Crystal oscillator output to ADC is enable.
End of enumeration elements list.
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