Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x7B4 byte (0x0)
mem_usage : registers
protection : not protected
Input mux register for SCT0 input
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Capture select registers for TIMER1 inputs
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER1 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x10C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x11E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER2 inputs
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER2 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x1304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x142C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER1 inputs
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER1 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x1688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x17BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Input mux register for SCT0 input
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Pin interrupt select register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Selection for frequency measurement reference clock
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKIN : Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
bits : 0 - 4 (5 bit)
access : read-write
Selection for frequency measurement target clock
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKIN : Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
bits : 0 - 4 (5 bit)
access : read-write
Capture select registers for TIMER2 inputs
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER2 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x18F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER2 inputs
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER2 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Pin interrupt select register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Input mux register for SCT0 input
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
DMA0 output trigger selection to become DMA0 trigger
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Pin interrupt select register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Capture select registers for TIMER3 inputs
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER3 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Capture select registers for TIMER4 inputs
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER4 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Input mux register for SCT0 input
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Pin interrupt secure select register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.
bits : 0 - 5 (6 bit)
access : read-write
Pin interrupt select register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Input mux register for SCT0 input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Capture select registers for TIMER0 inputs
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER0 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
DMA0 output trigger selection to become DMA0 trigger
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Trigger select register for DMA0 channel
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
DMA1 output trigger selection to become DMA1 trigger
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Pin interrupt select register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Capture select registers for TIMER3 inputs
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER3 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Input mux register for SCT0 input
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Capture select registers for TIMER4 inputs
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER4 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Pin interrupt select register
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
DMA0 output trigger selection to become DMA0 trigger
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Pin interrupt secure select register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.
bits : 0 - 5 (6 bit)
access : read-write
Trigger select register for DMA1 channel
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Capture select registers for TIMER0 inputs
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER0 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Pin interrupt select register
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Trigger select register for DMA0 channel
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER3 inputs
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER3 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
DMA1 output trigger selection to become DMA1 trigger
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
DMA0 output trigger selection to become DMA0 trigger
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Capture select registers for TIMER4 inputs
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER4 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Pin interrupt select register
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTPIN : Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
bits : 0 - 6 (7 bit)
access : read-write
Enable DMA0 requests
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQ_ENA : Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
bits : 0 - 22 (23 bit)
access : read-write
Set one or several bits in DMA0_REQ_ENA register
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SET : Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register
bits : 0 - 22 (23 bit)
access : write-only
Clear one or several bits in DMA0_REQ_ENA register
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register
bits : 0 - 22 (23 bit)
access : write-only
Trigger select register for DMA0 channel
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Enable DMA1 requests
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQ_ENA : Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
bits : 0 - 9 (10 bit)
access : read-write
Set one or several bits in DMA1_REQ_ENA register
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SET : Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register
bits : 0 - 9 (10 bit)
access : write-only
Clear one or several bits in DMA1_REQ_ENA register
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register
bits : 0 - 9 (10 bit)
access : write-only
Enable DMA0 triggers
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITRIG_ENA : Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
bits : 0 - 21 (22 bit)
access : read-write
Set one or several bits in DMA0_ITRIG_ENA register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SET : Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA0_ITRIG_ENA register
bits : 0 - 21 (22 bit)
access : write-only
Clear one or several bits in DMA0_ITRIG_ENA register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_ITRIG_ENA register
bits : 0 - 21 (22 bit)
access : write-only
Enable DMA1 triggers
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITRIG_ENA : Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
bits : 0 - 14 (15 bit)
access : read-write
Set one or several bits in DMA1_ITRIG_ENA register
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SET : Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no change in DMA1_ITRIG_ENA register
bits : 0 - 14 (15 bit)
access : write-only
Clear one or several bits in DMA1_ITRIG_ENA register
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_ITRIG_ENA register
bits : 0 - 14 (15 bit)
access : write-only
Capture select registers for TIMER1 inputs
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER1 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Capture select registers for TIMER3 inputs
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER3 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER0 inputs
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER0 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Capture select registers for TIMER4 inputs
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER4 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
DMA1 output trigger selection to become DMA1 trigger
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Trigger select register for DMA0 channel
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0xA54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
DMA1 output trigger selection to become DMA1 trigger
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Trigger select register for DMA0 channel
address_offset : 0xB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Capture select registers for TIMER0 inputs
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER0 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Input mux register for SCT0 input
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_N : Input number to SCT0 inputs 0 to 6..
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
SCT_GPI0 function selected from IOCON register
0x1 : val1
SCT_GPI1 function selected from IOCON register
0x2 : val2
SCT_GPI2 function selected from IOCON register
0x3 : val3
SCT_GPI3 function selected from IOCON register
0x4 : val4
SCT_GPI4 function selected from IOCON register
0x5 : val5
SCT_GPI5 function selected from IOCON register
0x6 : val6
SCT_GPI6 function selected from IOCON register
0x7 : val7
SCT_GPI7 function selected from IOCON register
0x8 : val8
T0_OUT0 ctimer 0 match[0] output
0x9 : val9
T1_OUT0 ctimer 1 match[0] output
0xA : val10
T2_OUT0 ctimer 2 match[0] output
0xB : val11
T3_OUT0 ctimer 3 match[0] output
0xC : val12
T4_OUT0 ctimer 4 match[0] output
0xD : val13
ADC_IRQ interrupt request from ADC
0xE : val14
GPIOINT_BMATCH
0xF : val15
USB0_FRAME_TOGGLE
0x10 : val16
USB1_FRAME_TOGGLE
0x11 : val17
COMP_OUTPUT output from analog comparator
0x12 : val18
I2S_SHARED_SCK[0] output from I2S pin sharing
0x13 : val19
I2S_SHARED_SCK[1] output from I2S pin sharing
0x14 : val20
I2S_SHARED_WS[0] output from I2S pin sharing
0x15 : val21
I2S_SHARED_WS[1] output from I2S pin sharing
0x16 : val22
ARM_TXEV interrupt event from cpu0 or cpu1
0x17 : val23
DEBUG_HALTED from cpu0 or cpu1
0x18 : val24
None
0x19 : val24
None
0x1A : val24
None
0x1B : val24
None
0x1C : val24
None
0x1D : val24
None
0x1E : val24
None
0x1F : val24
None
End of enumeration elements list.
Capture select registers for TIMER2 inputs
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER2 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Capture select registers for TIMER1 inputs
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTSEL : Input number to TIMER1 capture inputs 0 to 4
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
CT_INP0 function selected from IOCON register
0x1 : val1
CT_INP1 function selected from IOCON register
0x2 : val2
CT_INP2 function selected from IOCON register
0x3 : val3
CT_INP3 function selected from IOCON register
0x4 : val4
CT_INP4 function selected from IOCON register
0x5 : val5
CT_INP5 function selected from IOCON register
0x6 : val6
CT_INP6 function selected from IOCON register
0x7 : val7
CT_INP7 function selected from IOCON register
0x8 : val8
CT_INP8 function selected from IOCON register
0x9 : val9
CT_INP9 function selected from IOCON register
0xA : val10
CT_INP10 function selected from IOCON register
0xB : val11
CT_INP11 function selected from IOCON register
0xC : val12
CT_INP12 function selected from IOCON register
0xD : val13
CT_INP13 function selected from IOCON register
0xE : val14
CT_INP14 function selected from IOCON register
0xF : val15
CT_INP15 function selected from IOCON register
0x10 : val16
CT_INP16 function selected from IOCON register
0x11 : val17
None
0x12 : val18
None
0x13 : val19
None
0x14 : val20
USB0_FRAME_TOGGLE
0x15 : val21
USB1_FRAME_TOGGLE
0x16 : val22
COMP_OUTPUT output from analog comparator
0x17 : val23
I2S_SHARED_WS[0] output from I2S pin sharing
0x18 : val24
I2S_SHARED_WS[1] output from I2S pin sharing
0x19 : val25
None
0x1A : val25
None
0x1B : val25
None
0x1C : val25
None
0x1D : val25
None
0x1E : val25
None
0x1F : val25
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0xC68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA1 channel
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER2 Match 0
0x7 : val7
Timer CTIMER4 Match 0
0x8 : val8
DMA1 output trigger mux 0
0x9 : val9
DMA1 output trigger mux 1
0xA : val10
DMA1 output trigger mux 2
0xB : val11
DMA1 output trigger mux 3
0xC : val12
SCT0 DMA request 0
0xD : val13
SCT0 DMA request 1
0xE : val14
HASH DMA RX trigger
0xF : val15
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0xE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
Trigger select register for DMA0 channel
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP : Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : val0
Pin interrupt 0
0x1 : val1
Pin interrupt 1
0x2 : val2
Pin interrupt 2
0x3 : val3
Pin interrupt 3
0x4 : val4
Timer CTIMER0 Match 0
0x5 : val5
Timer CTIMER0 Match 1
0x6 : val6
Timer CTIMER1 Match 0
0x7 : val7
Timer CTIMER1 Match 1
0x8 : val8
Timer CTIMER2 Match 0
0x9 : val9
Timer CTIMER2 Match 1
0xA : val10
Timer CTIMER3 Match 0
0xB : val11
Timer CTIMER3 Match 1
0xC : val12
Timer CTIMER4 Match 0
0xD : val13
Timer CTIMER4 Match 1
0xE : val14
COMP_OUTPUT
0xF : val15
DMA0 output trigger mux 0
0x10 : val16
DMA0 output trigger mux 1
0x11 : val17
DMA0 output trigger mux 1
0x12 : val18
DMA0 output trigger mux 3
0x13 : val19
SCT0 DMA request 0
0x14 : val20
SCT0 DMA request 1
0x15 : val21
HASH DMA RX trigger
0x16 : val22
None
0x17 : val22
None
0x18 : val22
None
0x19 : val22
None
0x1A : val22
None
0x1B : val22
None
0x1C : val22
None
0x1D : val22
None
0x1E : val22
None
0x1F : val22
None
End of enumeration elements list.
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