Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected
VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset]
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGLVL : BoD trigger level.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : V_1P00
1.00 V.
0x1 : V_1P10
1.10 V.
0x2 : V_1P20
1.20 V.
0x3 : V_1P30
1.30 V.
0x4 : V_1P40
1.40 V.
0x5 : V_1P50
1.50 V.
0x6 : V_1P60
1.60 V.
0x7 : V_1P65
1.65 V.
0x8 : V_1P70
1.70 V.
0x9 : V_1P75
1.75 V.
0xA : V_1P80
1.80 V.
0xB : V_1P90
1.90 V.
0xC : V_2P00
2.00 V.
0xD : V_2P10
2.10 V.
0xE : V_2P20
2.20 V.
0xF : V_2P30
2.30 V.
0x10 : V_2P40
2.40 V.
0x11 : V_2P50
2.50 V.
0x12 : V_2P60
2.60 V.
0x13 : V_2P70
2.70 V.
0x14 : V_2P80
2.806 V.
0x15 : V_2P90
2.90 V.
0x16 : V_3P00
3.00 V.
0x17 : V_3P10
3.10 V.
0x18 : V_3P20
3.20 V.
0x19 : V_3P30_2
3.30 V.
0x1A : V_3P30_3
3.30 V.
0x1B : V_3P30_4
3.30 V.
0x1C : V_3P30_5
3.30 V.
0x1D : V_3P30_6
3.30 V.
0x1E : V_3P30_7
3.30 V.
0x1F : V_3P30_8
3.30 V.
End of enumeration elements list.
HYST : BoD Hysteresis control.
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : HYST_25MV
25 mV.
0x1 : HYST_50MV
50 mV.
0x2 : HYST_75MV
75 mV.
0x3 : HYST_100MV
100 mV.
End of enumeration elements list.
Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset]
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYST : Hysteris when hyst = '1'.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Hysteresis is disable.
0x1 : ENABLE
Hysteresis is enable.
End of enumeration elements list.
VREFINPUT : Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INTERNALREF
Select internal VREF.
0x1 : VDDA
Select VDDA.
End of enumeration elements list.
LOWPOWER : Low power mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : HIGHSPEED
High speed mode.
0x1 : LOWSPEED
Low power mode (Low speed).
End of enumeration elements list.
PMUX : Control word for P multiplexer:.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : VREF
VREF (See fiedl VREFINPUT).
0x1 : CMP0_A
Pin P0_0.
0x2 : CMP0_B
Pin P0_9.
0x3 : CMP0_C
Pin P0_18.
0x4 : CMP0_D
Pin P1_14.
0x5 : CMP0_E
Pin P2_23.
End of enumeration elements list.
NMUX : Control word for N multiplexer:.
bits : 7 - 9 (3 bit)
access : read-write
Enumeration:
0 : VREF
VREF (See field VREFINPUT).
0x1 : CMP0_A
Pin P0_0.
0x2 : CMP0_B
Pin P0_9.
0x3 : CMP0_C
Pin P0_18.
0x4 : CMP0_D
Pin P1_14.
0x5 : CMP0_E
Pin P2_23.
End of enumeration elements list.
VREF : Control reference voltage step, per steps of (VREFINPUT/31).
bits : 10 - 14 (5 bit)
access : read-write
FILTERCGF_SAMPLEMODE : Control the filtering of the Analog Comparator output.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : BYPASS
Bypass mode.
0x1 : FILTER1CLK
Filter 1 clock period.
0x2 : FILTER2CLK
Filter 2 clock period.
0x3 : FILTER3CLK
Filter 3 clock period.
End of enumeration elements list.
FILTERCGF_CLKDIV : Filter Clock divider.
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0 : FILTER_1CLK_PERIOD
Filter clock period duration equals 1 Analog Comparator clock period.
0x1 : FILTER_2CLK_PERIOD
Filter clock period duration equals 2 Analog Comparator clock period.
0x2 : FILTER_4CLK_PERIOD
Filter clock period duration equals 4 Analog Comparator clock period.
0x3 : FILTER_8CLK_PERIOD
Filter clock period duration equals 8 Analog Comparator clock period.
0x4 : FILTER_16CLK_PERIOD
Filter clock period duration equals 16 Analog Comparator clock period.
0x5 : FILTER_32CLK_PERIOD
Filter clock period duration equals 32 Analog Comparator clock period.
0x6 : FILTER_64CLK_PERIOD
Filter clock period duration equals 64 Analog Comparator clock period.
0x7 : FILTER_128CLK_PERIOD
Filter clock period duration equals 128 Analog Comparator clock period.
End of enumeration elements list.
Allows to identify the Wake-up I/O source from Deep Power Down mode
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUP0 : Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOEVENT
Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.
0x1 : EVENT
Last wake up from Deep Power down mode was triggred by wake up I/O 0.
End of enumeration elements list.
WAKEUP1 : Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOEVENT
Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.
0x1 : EVENT
Last wake up from Deep Power down mode was triggred by wake up I/O 1.
End of enumeration elements list.
WAKEUP2 : Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOEVENT
Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.
0x1 : EVENT
Last wake up from Deep Power down mode was triggred by wake up I/O 2.
End of enumeration elements list.
WAKEUP3 : Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOEVENT
Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.
0x1 : EVENT
Last wake up from Deep Power down mode was triggred by wake up I/O 3.
End of enumeration elements list.
FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset]
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL32KOK : XTAL oscillator 32 K OK signal.
bits : 0 - 0 (1 bit)
access : read-only
XTAL32KOSCFAILURE : XTAL32 KHZ oscillator oscillation failure detection indicator.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOFAIL
No oscillation failure has been detetced since the last time this bit has been cleared..
0x1 : FAILURE
At least one oscillation failure has been detetced since the last time this bit has been cleared..
End of enumeration elements list.
Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPDWAKEUPRESETENABLE : Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Reset event from DEEP POWER DOWN mode is disable.
0x1 : ENABLE
Reset event from DEEP POWER DOWN mode is enable.
End of enumeration elements list.
SWRRESETENABLE : Software reset enable.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Software reset is disable.
0x1 : ENABLE
Software reset is enable.
End of enumeration elements list.
BODVBATRESETENA_SECURE : BOD VBAT reset enable.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Any other value than b10, BOD VBAT reset is enable.
0x2 : DISABLE
BOD VBAT reset is disable.
End of enumeration elements list.
BODCORERESETENA_SECURE : BOD Core reset enable.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Any other value than b10, BOD Core reset is enable.
0x2 : DISABLE
BOD Core reset is disable.
End of enumeration elements list.
BODVBATRESETENA_SECURE_DP : BOD VBAT reset enable.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Any other value than b10, BOD VBAT reset is enable.
0x2 : DISABLE
BOD VBAT reset is disable.
End of enumeration elements list.
BODCORERESETENA_SECURE_DP : BOD Core reset enable.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Any other value than b10, BOD Core reset is enable.
0x2 : DISABLE
BOD Core reset is disable.
End of enumeration elements list.
General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset]
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR : The last chip reset was caused by a Power On Reset.
bits : 4 - 4 (1 bit)
access : read-write
PADRESET : The last chip reset was caused by a Pin Reset.
bits : 5 - 5 (1 bit)
access : read-write
BODRESET : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD.
bits : 6 - 6 (1 bit)
access : read-write
SYSTEMRESET : The last chip reset was caused by a System Reset requested by the ARM CPU.
bits : 7 - 7 (1 bit)
access : read-write
WDTRESET : The last chip reset was caused by the Watchdog Timer.
bits : 8 - 8 (1 bit)
access : read-write
SWRRESET : The last chip reset was caused by a Software event.
bits : 9 - 9 (1 bit)
access : read-write
DPDRESET_WAKEUPIO : The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode.
bits : 10 - 10 (1 bit)
access : read-write
DPDRESET_RTC : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode.
bits : 11 - 11 (1 bit)
access : read-write
DPDRESET_OSTIMER : The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode.
bits : 12 - 12 (1 bit)
access : read-write
BOOTERRORCOUNTER : ROM Boot Fatal Error Counter.
bits : 16 - 19 (4 bit)
access : read-write
RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset]
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) .
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FRO32K
FRO 32 KHz.
0x1 : XTAL32K
XTAL 32KHz.
End of enumeration elements list.
CLK1KHZDIV : Actual division ratio is : 28 + CLK1KHZDIV.
bits : 1 - 3 (3 bit)
access : read-write
CLK1KHZDIVUPDATEREQ : RTC 1KHz clock Divider status flag.
bits : 15 - 15 (1 bit)
access : read-write
CLK1HZDIV : Actual division ratio is : 31744 + CLK1HZDIV.
bits : 16 - 26 (11 bit)
access : read-write
CLK1HZDIVHALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
CLK1HZDIVUPDATEREQ : RTC 1Hz Divider status flag.
bits : 31 - 31 (1 bit)
access : read-write
OS Timer control register [Reset by: PoR, Brown Out Detectors Reset]
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFTRESET : Active high reset.
bits : 0 - 0 (1 bit)
access : read-write
CLOCKENABLE : Enable OSTIMER 32 KHz clock.
bits : 1 - 1 (1 bit)
access : read-write
DPDWAKEUPENABLE : Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).
bits : 2 - 2 (1 bit)
access : read-write
OSC32KPD : Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K.
bits : 3 - 3 (1 bit)
access : read-write
OSTIMERCLKSEL : OS event timer clock select.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Oscillator 32 kHz clock.
0x1 : ENUM_0x1
FRO 1MHz clock.
0x2 : ENUM_0x2
Main clock for OS timer.
0x3 : ENUM_0x3
No clock.
End of enumeration elements list.
Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset]
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDEN_BODVBAT : Controls power to VBAT Brown Out Detector (BOD).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
BOD VBAT is powered.
0x1 : POWEREDOFF
BOD VBAT is powered down.
End of enumeration elements list.
PDEN_FRO32K : Controls power to the Free Running Oscillator (FRO) 32 KHz.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
FRO32KHz is powered.
0x1 : POWEREDOFF
FRO32KHz is powered down.
End of enumeration elements list.
PDEN_XTAL32K : Controls power to crystal 32 KHz.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
Crystal 32KHz is powered.
0x1 : POWEREDOFF
Crystal 32KHz is powered down.
End of enumeration elements list.
PDEN_XTAL32M : Controls power to high speed crystal.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
High speed crystal is powered.
0x1 : POWEREDOFF
High speed crystal is powered down.
End of enumeration elements list.
PDEN_PLL0 : Controls power to System PLL (also refered as PLL0).
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
PLL0 is powered.
0x1 : POWEREDOFF
PLL0 is powered down.
End of enumeration elements list.
PDEN_PLL1 : Controls power to USB PLL (also refered as PLL1).
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
PLL1 is powered.
0x1 : POWEREDOFF
PLL1 is powered down.
End of enumeration elements list.
PDEN_USBFSPHY : Controls power to USB Full Speed phy.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
USB Full Speed phy is powered.
0x1 : POWEREDOFF
USB Full Speed phy is powered down.
End of enumeration elements list.
PDEN_USBHSPHY : Controls power to USB High Speed Phy.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
USB HS phy is powered.
0x1 : POWEREDOFF
USB HS phy is powered down.
End of enumeration elements list.
PDEN_COMP : Controls power to Analog Comparator.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
Analog Comparator is powered.
0x1 : POWEREDOFF
Analog Comparator is powered down.
End of enumeration elements list.
PDEN_LDOUSBHS : Controls power to USB high speed LDO.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
USB high speed LDO is powered.
0x1 : POWEREDOFF
USB high speed LDO is powered down.
End of enumeration elements list.
PDEN_AUXBIAS : Controls power to auxiliary biasing (AUXBIAS)
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
auxiliary biasing is powered.
0x1 : POWEREDOFF
auxiliary biasing is powered down.
End of enumeration elements list.
PDEN_LDOXO32M : Controls power to high speed crystal LDO.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
High speed crystal LDO is powered.
0x1 : POWEREDOFF
High speed crystal LDO is powered down.
End of enumeration elements list.
PDEN_RNG : Controls power to all True Random Number Genetaor (TRNG) clock sources.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
TRNG clocks are powered.
0x1 : POWEREDOFF
TRNG clocks are powered down.
End of enumeration elements list.
PDEN_PLL0_SSCG : Controls power to System PLL (PLL0) Spread Spectrum module.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : POWEREDON
PLL0 Sread spectrum module is powered.
0x1 : POWEREDOFF
PLL0 Sread spectrum module is powered down.
End of enumeration elements list.
Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset]
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PDRUNCFGSET0 : Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset]
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PDRUNCFGCLR0 : Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
bits : 0 - 31 (32 bit)
access : write-only
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