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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

SUBSEC

GPREG[2]

GPREG[3]

GPREG[4]

GPREG[5]

GPREG[6]

GPREG[7]

MATCH

COUNT

GPREG[0]

WAKE

GPREG[1]


CTRL

RTC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRESET ALARM1HZ WAKE1KHZ ALARMDPD_EN WAKEDPD_EN RTC1KHZ_EN RTC_EN RTC_OSC_PD RTC_OSC_BYPASS RTC_SUBSEC_ENA

SWRESET : Software reset control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_IN_RESET

Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.

0x1 : IN_RESET

In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared.

End of enumeration elements list.

ALARM1HZ : RTC 1 Hz timer alarm flag status.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NO_MATCH

No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.

0x1 : MATCH

Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.

End of enumeration elements list.

WAKE1KHZ : RTC 1 kHz timer wake-up flag status.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : RUN

Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.

0x1 : TIMEOUT

Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.

End of enumeration elements list.

ALARMDPD_EN : RTC 1 Hz timer alarm enable for Deep power-down.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.

0x1 : ENABLE

Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.

End of enumeration elements list.

WAKEDPD_EN : RTC 1 kHz timer wake-up enable for Deep power-down.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.

0x1 : ENABLE

Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.

End of enumeration elements list.

RTC1KHZ_EN : RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.

0x1 : ENABLE

Enable. The 1 kHz RTC timer is enabled.

End of enumeration elements list.

RTC_EN : RTC enable.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.

0x1 : ENABLE

Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.

End of enumeration elements list.

RTC_OSC_PD : RTC oscillator power-down control.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : POWER_UP

See RTC_OSC_BYPASS

0x1 : POWERED_DOWN

RTC oscillator is powered-down.

End of enumeration elements list.

RTC_OSC_BYPASS : RTC oscillator bypass control.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : USED

The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins.

0x1 : BYPASS

The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin.

End of enumeration elements list.

RTC_SUBSEC_ENA : RTC Sub-second counter control.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : POWER_UP

The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'.

0x1 : POWERED_DOWN

The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode.

End of enumeration elements list.


SUBSEC

Sub-second counter register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBSEC SUBSEC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBSEC

SUBSEC : A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes.
bits : 0 - 14 (15 bit)
access : read-only


GPREG[2]

General Purpose register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[2] GPREG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[3]

General Purpose register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[3] GPREG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[4]

General Purpose register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[4] GPREG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[5]

General Purpose register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[5] GPREG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[6]

General Purpose register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[6] GPREG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[7]

General Purpose register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[7] GPREG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


MATCH

RTC match register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MATCH MATCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATVAL

MATVAL : Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
bits : 0 - 31 (32 bit)
access : read-write


COUNT

RTC counter register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after the RTC_EN bit is set.
bits : 0 - 31 (32 bit)
access : read-write


GPREG[0]

General Purpose register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[0] GPREG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write


WAKE

High-resolution/wake-up timer control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE WAKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence. Do not write to this register while counting is in progress.
bits : 0 - 15 (16 bit)
access : read-write


GPREG[1]

General Purpose register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPREG[1] GPREG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPDATA

GPDATA : Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
bits : 0 - 31 (32 bit)
access : read-write



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