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PRINCE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x94 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ENC_ENABLE

IV_LSB0

IV_MSB0

BASE_ADDR0

SR_ENABLE0

IV_LSB1

IV_MSB1

BASE_ADDR1

SR_ENABLE1

IV_LSB2

IV_MSB2

BASE_ADDR2

SR_ENABLE2

MASK_LSB

MASK_MSB

ERR

LOCK


ENC_ENABLE

Encryption Enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENC_ENABLE ENC_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enables PRINCE encryption for flash programming.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Encryption of writes to the flash controller DATAW* registers is disabled.

0x1 : ENABLED

Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled.

End of enumeration elements list.


IV_LSB0

Initial Vector register for region 0, Least Significant Bits
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_LSB0 IV_LSB0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


IV_MSB0

Initial Vector register for region 0, Most Significant Bits
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_MSB0 IV_MSB0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


BASE_ADDR0

Base Address for region 0 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_ADDR0 BASE_ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_FIXED ADDR_PRG

ADDR_FIXED : Fixed portion of the base address of region 0.
bits : 0 - 17 (18 bit)
access : read-only

ADDR_PRG : Programmable portion of the base address of region 0.
bits : 18 - 19 (2 bit)
access : read-write


SR_ENABLE0

Sub-Region Enable register for region 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR_ENABLE0 SR_ENABLE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.
bits : 0 - 31 (32 bit)
access : read-write


IV_LSB1

Initial Vector register for region 1, Least Significant Bits
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_LSB1 IV_LSB1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


IV_MSB1

Initial Vector register for region 1, Most Significant Bits
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_MSB1 IV_MSB1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


BASE_ADDR1

Base Address for region 1 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_ADDR1 BASE_ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_FIXED ADDR_PRG

ADDR_FIXED : Fixed portion of the base address of region 1.
bits : 0 - 17 (18 bit)
access : read-only

ADDR_PRG : Programmable portion of the base address of region 1.
bits : 18 - 19 (2 bit)
access : read-write


SR_ENABLE1

Sub-Region Enable register for region 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR_ENABLE1 SR_ENABLE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.
bits : 0 - 31 (32 bit)
access : read-write


IV_LSB2

Initial Vector register for region 2, Least Significant Bits
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_LSB2 IV_LSB2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


IV_MSB2

Initial Vector register for region 2, Most Significant Bits
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IV_MSB2 IV_MSB2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IVVAL

IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only


BASE_ADDR2

Base Address for region 2 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE_ADDR2 BASE_ADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_FIXED ADDR_PRG

ADDR_FIXED : Fixed portion of the base address of region 2.
bits : 0 - 17 (18 bit)
access : read-only

ADDR_PRG : Programmable portion of the base address of region 2.
bits : 18 - 19 (2 bit)
access : read-write


SR_ENABLE2

Sub-Region Enable register for region 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR_ENABLE2 SR_ENABLE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.
bits : 0 - 31 (32 bit)
access : read-write


MASK_LSB

Data Mask register, 32 Least Significant Bits
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MASK_LSB MASK_LSB write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASKVAL

MASKVAL : Value of the 32 Least Significant Bits of the 64-bit data mask.
bits : 0 - 31 (32 bit)
access : write-only


MASK_MSB

Data Mask register, 32 Most Significant Bits
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MASK_MSB MASK_MSB write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASKVAL

MASKVAL : Value of the 32 Most Significant Bits of the 64-bit data mask.
bits : 0 - 31 (32 bit)
access : write-only


ERR

Error status register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERR ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRSTAT

ERRSTAT : PRINCE Error Status. This bit is write-1 to clear.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

No PRINCE error.

0x1 : ERROR

Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1.

End of enumeration elements list.


LOCK

Lock register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKREG0 LOCKREG1 LOCKREG2 LOCKMASK

LOCKREG0 : Lock Region 0 registers.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..

0x1 : ENABLED

Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..

End of enumeration elements list.

LOCKREG1 : Lock Region 1 registers.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..

0x1 : ENABLED

Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..

End of enumeration elements list.

LOCKREG2 : Lock Region 2 registers.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..

0x1 : ENABLED

Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..

End of enumeration elements list.

LOCKMASK : Lock the Mask registers.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled. MASK_LSB, and MASK_MSB are writable..

0x1 : ENABLED

Enabled. MASK_LSB, and MASK_MSB are not writable..

End of enumeration elements list.



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