\n
address_offset : 0x0 Bytes (0x0)
size : 0x94 byte (0x0)
mem_usage : registers
protection : not protected
Encryption Enable register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enables PRINCE encryption for flash programming.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Encryption of writes to the flash controller DATAW* registers is disabled.
0x1 : ENABLED
Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled.
End of enumeration elements list.
Initial Vector register for region 0, Least Significant Bits
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Initial Vector register for region 0, Most Significant Bits
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Base Address for region 0 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_FIXED : Fixed portion of the base address of region 0.
bits : 0 - 17 (18 bit)
access : read-only
ADDR_PRG : Programmable portion of the base address of region 0.
bits : 18 - 19 (2 bit)
access : read-write
Sub-Region Enable register for region 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.
bits : 0 - 31 (32 bit)
access : read-write
Initial Vector register for region 1, Least Significant Bits
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Initial Vector register for region 1, Most Significant Bits
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Base Address for region 1 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_FIXED : Fixed portion of the base address of region 1.
bits : 0 - 17 (18 bit)
access : read-only
ADDR_PRG : Programmable portion of the base address of region 1.
bits : 18 - 19 (2 bit)
access : read-write
Sub-Region Enable register for region 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.
bits : 0 - 31 (32 bit)
access : read-write
Initial Vector register for region 2, Least Significant Bits
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Initial Vector register for region 2, Most Significant Bits
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IVVAL : Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
bits : 0 - 31 (32 bit)
access : write-only
Base Address for region 2 register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR_FIXED : Fixed portion of the base address of region 2.
bits : 0 - 17 (18 bit)
access : read-only
ADDR_PRG : Programmable portion of the base address of region 2.
bits : 18 - 19 (2 bit)
access : read-write
Sub-Region Enable register for region 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.
bits : 0 - 31 (32 bit)
access : read-write
Data Mask register, 32 Least Significant Bits
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Value of the 32 Least Significant Bits of the 64-bit data mask.
bits : 0 - 31 (32 bit)
access : write-only
Data Mask register, 32 Most Significant Bits
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Value of the 32 Most Significant Bits of the 64-bit data mask.
bits : 0 - 31 (32 bit)
access : write-only
Error status register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRSTAT : PRINCE Error Status. This bit is write-1 to clear.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_ERROR
No PRINCE error.
0x1 : ERROR
Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1.
End of enumeration elements list.
Lock register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKREG0 : Lock Region 0 registers.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..
0x1 : ENABLED
Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..
End of enumeration elements list.
LOCKREG1 : Lock Region 1 registers.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..
0x1 : ENABLED
Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..
End of enumeration elements list.
LOCKREG2 : Lock Region 2 registers.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..
0x1 : ENABLED
Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..
End of enumeration elements list.
LOCKMASK : Lock the Mask registers.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. MASK_LSB, and MASK_MSB are writable..
0x1 : ENABLED
Enabled. MASK_LSB, and MASK_MSB are not writable..
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.