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address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV : Revision.
bits : 0 - 7 (8 bit)
access : read-only
Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : Scheduling Overrun interrupt.
bits : 0 - 0 (1 bit)
access : read-write
WDH : HcDoneHead Writeback interrupt.
bits : 1 - 1 (1 bit)
access : read-write
SF : Start of Frame interrupt.
bits : 2 - 2 (1 bit)
access : read-write
RD : Resume Detect interrupt.
bits : 3 - 3 (1 bit)
access : read-write
UE : Unrecoverable Error interrupt.
bits : 4 - 4 (1 bit)
access : read-write
FNO : Frame Number Overflow interrupt.
bits : 5 - 5 (1 bit)
access : read-write
RHSC : Root Hub Status Change interrupt.
bits : 6 - 6 (1 bit)
access : read-write
OC : Ownership Change interrupt.
bits : 30 - 30 (1 bit)
access : read-write
MIE : Master Interrupt Enable.
bits : 31 - 31 (1 bit)
access : read-write
The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : Scheduling Overrun interrupt.
bits : 0 - 0 (1 bit)
access : read-write
WDH : HcDoneHead Writeback interrupt.
bits : 1 - 1 (1 bit)
access : read-write
SF : Start of Frame interrupt.
bits : 2 - 2 (1 bit)
access : read-write
RD : Resume Detect interrupt.
bits : 3 - 3 (1 bit)
access : read-write
UE : Unrecoverable Error interrupt.
bits : 4 - 4 (1 bit)
access : read-write
FNO : Frame Number Overflow interrupt.
bits : 5 - 5 (1 bit)
access : read-write
RHSC : Root Hub Status Change interrupt.
bits : 6 - 6 (1 bit)
access : read-write
OC : Ownership Change interrupt.
bits : 30 - 30 (1 bit)
access : read-write
MIE : A 0 written to this field is ignored by HC.
bits : 31 - 31 (1 bit)
access : read-write
Contains the physical address of the host controller communication area
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCCA : Base address of the Host Controller Communication Area.
bits : 8 - 31 (24 bit)
access : read-write
Contains the physical address of the current isochronous or interrupt endpoint descriptor
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCED : The content of this register is updated by HC after a periodic ED is processed.
bits : 4 - 31 (28 bit)
access : read-only
Contains the physical address of the first endpoint descriptor of the control list
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHED : HC traverses the Control list starting with the HcControlHeadED pointer.
bits : 4 - 31 (28 bit)
access : read-write
Contains the physical address of the current endpoint descriptor of the control list
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCED : ControlCurrentED.
bits : 4 - 31 (28 bit)
access : read-write
Contains the physical address of the first endpoint descriptor of the bulk list
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BHED : BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
bits : 4 - 31 (28 bit)
access : read-write
Contains the physical address of the current endpoint descriptor of the bulk list
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCED : BulkCurrentED This is advanced to the next ED after the HC has served the current one.
bits : 4 - 31 (28 bit)
access : read-write
Contains the physical address of the last transfer descriptor added to the 'Done' queue
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DH : DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
bits : 4 - 31 (28 bit)
access : read-only
Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FI : FrameInterval This specifies the interval between two consecutive SOFs in bit times.
bits : 0 - 13 (14 bit)
access : read-write
FSMPS : FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame.
bits : 16 - 30 (15 bit)
access : read-write
FIT : FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
bits : 31 - 31 (1 bit)
access : read-write
A 14-bit counter showing the bit time remaining in the current frame
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FR : FrameRemaining This counter is decremented at each bit time.
bits : 0 - 13 (14 bit)
access : read-only
FRT : FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0.
bits : 31 - 31 (1 bit)
access : read-only
Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FN : FrameNumber This is incremented when HcFmRemaining is re-loaded.
bits : 0 - 15 (16 bit)
access : read-only
Defines the operating modes of the HC
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CBSR : ControlBulkServiceRatio.
bits : 0 - 1 (2 bit)
access : read-write
PLE : PeriodicListEnable.
bits : 2 - 2 (1 bit)
access : read-write
IE : IsochronousEnable.
bits : 3 - 3 (1 bit)
access : read-write
CLE : ControlListEnable.
bits : 4 - 4 (1 bit)
access : read-write
BLE : BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
bits : 5 - 5 (1 bit)
access : read-write
HCFS : HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin 1 ms later.
bits : 6 - 7 (2 bit)
access : read-write
IR : InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
bits : 8 - 8 (1 bit)
access : read-write
RWC : RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
bits : 9 - 9 (1 bit)
access : read-write
RWE : RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling.
bits : 10 - 10 (1 bit)
access : read-write
Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
bits : 0 - 13 (14 bit)
access : read-write
Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LST : LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction.
bits : 0 - 11 (12 bit)
access : read-write
First of the two registers which describes the characteristics of the root hub
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDP : NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
bits : 0 - 7 (8 bit)
access : read-write
PSM : PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
bits : 8 - 8 (1 bit)
access : read-write
NPS : NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
bits : 9 - 9 (1 bit)
access : read-write
DT : DeviceType This bit specifies that the root hub is not a compound device.
bits : 10 - 10 (1 bit)
access : read-write
OCPM : OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
bits : 11 - 11 (1 bit)
access : read-write
NOCP : NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
bits : 12 - 12 (1 bit)
access : read-write
POTPGT : PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub.
bits : 24 - 31 (8 bit)
access : read-write
Second of the two registers which describes the characteristics of the Root Hub
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : DeviceRemovable Each bit is dedicated to a port of the Root Hub.
bits : 0 - 15 (16 bit)
access : read-write
PPCM : PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set.
bits : 16 - 31 (16 bit)
access : read-write
This register is divided into two parts
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPS : (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as 0.
bits : 0 - 0 (1 bit)
access : read-write
OCI : OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
bits : 1 - 1 (1 bit)
access : read-write
DRWE : (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt.
bits : 15 - 15 (1 bit)
access : read-write
LPSC : (read) LocalPowerStatusChange The root hub does not support the local power status feature.
bits : 16 - 16 (1 bit)
access : read-write
OCIC : OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
bits : 17 - 17 (1 bit)
access : read-write
CRWE : (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
bits : 31 - 31 (1 bit)
access : read-write
Controls and reports the port events on a per-port basis
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCS : (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
bits : 0 - 0 (1 bit)
access : read-write
PES : (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
bits : 1 - 1 (1 bit)
access : read-write
PSS : (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
bits : 2 - 2 (1 bit)
access : read-write
POCI : (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis.
bits : 3 - 3 (1 bit)
access : read-write
PRS : (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
bits : 4 - 4 (1 bit)
access : read-write
PPS : (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type of power switching implemented.
bits : 8 - 8 (1 bit)
access : read-write
LSDA : (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
bits : 9 - 9 (1 bit)
access : read-write
CSC : ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
bits : 16 - 16 (1 bit)
access : read-write
PESC : PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
bits : 17 - 17 (1 bit)
access : read-write
PSSC : PortSuspendStatusChange This bit is set when the full resume sequence is completed.
bits : 18 - 18 (1 bit)
access : read-write
OCIC : PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
bits : 19 - 19 (1 bit)
access : read-write
PRSC : PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
bits : 20 - 20 (1 bit)
access : read-write
Controls the port if it is attached to the host block or the device block
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Port ID pin value.
bits : 0 - 0 (1 bit)
access : read-write
ID_EN : Port ID pin pull-up enable.
bits : 8 - 8 (1 bit)
access : read-write
DEV_ENABLE : 1: device 0: host.
bits : 16 - 16 (1 bit)
access : read-write
This register is used to receive the commands from the Host Controller Driver (HCD)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCR : HostControllerReset This bit is set by HCD to initiate a software reset of HC.
bits : 0 - 0 (1 bit)
access : read-write
CLF : ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
bits : 1 - 1 (1 bit)
access : read-write
BLF : BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
bits : 2 - 2 (1 bit)
access : read-write
OCR : OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
bits : 3 - 3 (1 bit)
access : read-write
SOC : SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
bits : 6 - 7 (2 bit)
access : read-write
Indicates the status on various events that cause hardware interrupts by setting the appropriate bits
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SO : SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber.
bits : 0 - 0 (1 bit)
access : read-write
WDH : WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
bits : 1 - 1 (1 bit)
access : read-write
SF : StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
bits : 2 - 2 (1 bit)
access : read-write
RD : ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
bits : 3 - 3 (1 bit)
access : read-write
UE : UnrecoverableError This bit is set when HC detects a system error not related to USB.
bits : 4 - 4 (1 bit)
access : read-write
FNO : FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
bits : 5 - 5 (1 bit)
access : read-write
RHSC : RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed.
bits : 6 - 6 (1 bit)
access : read-write
OC : OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
bits : 10 - 31 (22 bit)
access : read-write
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