Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
The SCR controls features of entry to and exit from low-power state.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. This bit is banked between Security states.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_SLEEP
Do not sleep when returning to Thread mode.
0x1 : SLEEP
Enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low-power mode. This bit is not banked between Security states.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SLEEP
Sleep.
0x1 : DEEP_SLEEP
Deep sleep.
End of enumeration elements list.
SLEEPDEEPS : Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit in only accessible from the Secure state, and behaves as RAZ/WI when accessed from the Nonsecure state. This bit is not banked between Security states.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_AND_NON_SECURE
The SLEEPDEEP bit is accessible from both Security states.
0x1 : SECURE_ONLY
The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state.
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. This bit is banked between Security states.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : EXCLUDE_DISABLED_INTERRUPTS
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
0x1 : INCLUDE_DISABLED_INTERRUPTS
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
System Handler Control and State Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : MemManage exception active.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
MemManage exception is not active.
0x1 : ACTIVE
MemManage exception is active.
End of enumeration elements list.
BUSFAULTACT : BusFault exception active.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
BusFault exception is not active.
0x1 : ACTIVE
BusFault exception is active.
End of enumeration elements list.
HARDFAULTACT : HardFault exception active.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
HardFault exception is not active.
0x1 : ACTIVE
HardFault exception is active.
End of enumeration elements list.
USGFAULTACT : UsageFault exception active.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
UsageFault exception is not active.
0x1 : ACTIVE
UsageFault exception is active.
End of enumeration elements list.
SECUREFAULTACT : SecureFault exception active
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
SecureFault exception is not active.
0x1 : ACTIVE
SecureFault exception is active.
End of enumeration elements list.
NMIACT : NMI exception active.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
NMI exception is not active.
0x1 : ACTIVE
NMI exception is active.
End of enumeration elements list.
SVCALLACT : SVCall active.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
SVCall exception is not active.
0x1 : ACTIVE
SVCall exception is active.
End of enumeration elements list.
MONITORACT : Debug monitor active.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
Debug monitor exception is not active.
0x1 : ACTIVE
Debug monitor exception is active.
End of enumeration elements list.
PENDSVACT : PendSV exception active.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
PendSV exception is not active.
0x1 : ACTIVE
PendSV exception is active.
End of enumeration elements list.
SYSTICKACT : SysTick exception active.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
SysTick exception is not active.
0x1 : ACTIVE
SysTick exception is active.
End of enumeration elements list.
USGFAULTPENDED : UsageFault exception pending.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
UsageFault exception is not pending.
0x1 : PENDING
UsageFault exception is pending.
End of enumeration elements list.
MEMFAULTPENDED : MemManage exception pending.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
MemManage exception is not pending.
0x1 : PENDING
MemManage exception is pending.
End of enumeration elements list.
BUSFAULTPENDED : BusFault exception pending.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
BusFault exception is pending.
0x1 : PENDING
BusFault exception is not pending.
End of enumeration elements list.
SVCALLPENDED : SVCall pending.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
SVCall exception is not pending.
0x1 : PENDING
SVCall exception is pending.
End of enumeration elements list.
MEMFAULTENA : MemManage enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
MemManage exception is disabled.
0x1 : ENABLED
MemManage exception is enabled.
End of enumeration elements list.
BUSFAULTENA : BusFault enable.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
BusFault is disabled.
0x1 : ENABLED
BusFault is enabled.
End of enumeration elements list.
USGFAULTENA : UsageFault enable.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
UsageFault is disabled.
0x1 : ENABLED
UsageFault is enabled.
End of enumeration elements list.
SECUREFAULTENA : SecureFault exception enable.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
SecureFault exception is disabled.
0x1 : ENABLED
SecureFault exception is enabled.
End of enumeration elements list.
SECUREFAULTPENDED : SecureFault exception pended state bit.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
SecureFault exception modification is disabled.
0x1 : ENABLED
SecureFault exception modification is enabled.
End of enumeration elements list.
HARDFAULTPENDED : HardFault exception pended state
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
HardFault exception modification is disabled.
0x1 : ENABLED
HardFault exception modification is enabled.
End of enumeration elements list.
Non-secure Access Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : CP0 access.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP1 : CP1 access.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP2 : CP2 access.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP3 : CP3 access.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP4 : CP4 access.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP5 : CP5 access.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP6 : CP6 access.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP7 : CP7 access.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to this coprocessor generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to this coprocessor permitted.
End of enumeration elements list.
CP10 : CP10 access.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PERMITTED
Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault.
0x1 : PERMITTED
Non-secure access to the Floatingpoint Extension permitted.
End of enumeration elements list.
CP11 : CP11 access.
bits : 11 - 11 (1 bit)
access : read-write
Application Interrupt and Reset Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is UNPREDICTABLE. This bit is not banked between Security states.
bits : 1 - 1 (1 bit)
access : write-only
SYSRESETREQ : System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. RW if SYSRESETREQS is 0. When SYSRESETREQS is set to 1, from Non-secure state this bit acts as RAZ/WI.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NO_REQUEST
Do not request a system reset.
0x1 : REQUEST_RESET
Request a system reset.
End of enumeration elements list.
SYSRESETREQS : System reset request, Secure state only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states. RW from Secure State and RAZ/WI from Non-secure state.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_AND_NON_SECURE
SYSRESETREQ functionality is available to both Security states.
0x1 : SECURE_ONLY
SYSRESETREQ functionality is only available to Secure state.
End of enumeration elements list.
PRIGROUP : Interrupt priority grouping field. This field determines the split of group priority from subpriority. This bit is banked between Security states
bits : 8 - 10 (3 bit)
access : read-write
BFHFNMINS : BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. RW from Secure-state and RO from Non-secure state.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE
BusFault, HardFault, and NMI are Secure.
0x1 : NON_SECURE
BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
End of enumeration elements list.
PRIS : Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. This bit is not banked between Security states. RW from Secure state and RAZ/WI from Non-secure state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SAME_PRIORITY
Priority ranges of Secure and Non-secure exceptions are identical
0x1 : SECURE_PRIORITIZED
Non-secure exceptions are de-prioritized
End of enumeration elements list.
ENDIANNESS : Data endianness bit. This bit is not banked between Security states.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : LITTLE_ENDIAN
Little-endian.
0x1 : BIG_ENDIAN
Big-endian
End of enumeration elements list.
VECTKEY : Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. This Field is not banked between Security states.
bits : 16 - 31 (16 bit)
access : read-only
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