\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
command register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMD : command register.
bits : 0 - 31 (32 bit)
access : write-only
start (or only) address for next flash command
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTA : Address / Start address for commands that take an address (range) as a parameter.
bits : 0 - 17 (18 bit)
access : read-write
data register, word 0-7; Memory data, or command parameter, or command result.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : no description available
bits : 0 - 31 (32 bit)
access : read-write
end address for next flash command, if command operates on address ranges
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPA : Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range).
bits : 0 - 17 (18 bit)
access : read-write
data register, word 0-7; Memory data, or command parameter, or command result.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : no description available
bits : 0 - 31 (32 bit)
access : read-write
data register, word 0-7; Memory data, or command parameter, or command result.
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : no description available
bits : 0 - 31 (32 bit)
access : read-write
data register, word 0-7; Memory data, or command parameter, or command result.
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATAW : no description available
bits : 0 - 31 (32 bit)
access : read-write
event register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RST : When bit is set, the controller and flash are reset.
bits : 0 - 0 (1 bit)
access : write-only
WAKEUP : When bit is set, the controller wakes up from whatever low power or powerdown mode was active.
bits : 1 - 1 (1 bit)
access : write-only
ABORT : When bit is set, a running program/erase command is aborted.
bits : 2 - 2 (1 bit)
access : write-only
Clear interrupt enable bits
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FAIL : When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
bits : 0 - 0 (1 bit)
access : write-only
ERR : When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
bits : 1 - 1 (1 bit)
access : write-only
DONE : When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
bits : 2 - 2 (1 bit)
access : write-only
ECC_ERR : When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
bits : 3 - 3 (1 bit)
access : write-only
Set interrupt enable bits
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FAIL : When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
bits : 0 - 0 (1 bit)
access : write-only
ERR : When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
bits : 1 - 1 (1 bit)
access : write-only
DONE : When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
bits : 2 - 2 (1 bit)
access : write-only
ECC_ERR : When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
bits : 3 - 3 (1 bit)
access : write-only
Interrupt status bits
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAIL : This status bit is set if execution of a (legal) command failed.
bits : 0 - 0 (1 bit)
access : read-only
ERR : This status bit is set if execution of an illegal command is detected.
bits : 1 - 1 (1 bit)
access : read-only
DONE : This status bit is set at the end of command execution.
bits : 2 - 2 (1 bit)
access : read-only
ECC_ERR : This status bit is set if, during a memory read operation (either a user-requested read, or a speculative read, or reads performed by a controller command), a correctable or uncorrectable error is detected by ECC decoding logic.
bits : 3 - 3 (1 bit)
access : read-only
Interrupt enable bits
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAIL : If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
bits : 0 - 0 (1 bit)
access : read-only
ERR : If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
bits : 1 - 1 (1 bit)
access : read-only
DONE : If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
bits : 2 - 2 (1 bit)
access : read-only
ECC_ERR : If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
bits : 3 - 3 (1 bit)
access : read-only
Clear interrupt status bits
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FAIL : When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
bits : 0 - 0 (1 bit)
access : write-only
ERR : When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
bits : 1 - 1 (1 bit)
access : write-only
DONE : When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
bits : 2 - 2 (1 bit)
access : write-only
ECC_ERR : When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
bits : 3 - 3 (1 bit)
access : write-only
Set interrupt status bits
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FAIL : When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
bits : 0 - 0 (1 bit)
access : write-only
ERR : When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
bits : 1 - 1 (1 bit)
access : write-only
DONE : When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
bits : 2 - 2 (1 bit)
access : write-only
ECC_ERR : When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
bits : 3 - 3 (1 bit)
access : write-only
Controller+Memory module identification
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
APERTURE : Aperture i.
bits : 0 - 7 (8 bit)
access : read-only
MINOR_REV : Minor revision i.
bits : 8 - 11 (4 bit)
access : read-only
MAJOR_REV : Major revision i.
bits : 12 - 15 (4 bit)
access : read-only
ID : Identifier.
bits : 16 - 31 (16 bit)
access : read-only
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