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DMAMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

C0CR

C4CR

RG0CR

RG1CR

RG2CR

RG3CR

C14CR

C15CR

C5CR

RGSR

RGCFR

C6CR

C7CR

C8CR

C9CR

C10CR

C11CR

C12CR

C13CR

C1CR

C2CR

CSR

CCFR

C3CR


C0CR

DMA Multiplexer Channel 0 Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0CR C0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C4CR

DMA Multiplexer Channel 4 Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C4CR C4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


RG0CR

DMA Request Generator 0 Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG0CR RG0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal ID
bits : 0 - 4 (5 bit)

OIE : Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

GE : Generation Enable
bits : 16 - 16 (1 bit)

GPOL : Generation Polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of Request
bits : 19 - 23 (5 bit)


RG1CR

DMA Request Generator 1 Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG1CR RG1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal ID
bits : 0 - 4 (5 bit)

OIE : Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

GE : Generation Enable
bits : 16 - 16 (1 bit)

GPOL : Generation Polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of Request
bits : 19 - 23 (5 bit)


RG2CR

DMA Request Generator 2 Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG2CR RG2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal ID
bits : 0 - 4 (5 bit)

OIE : Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

GE : Generation Enable
bits : 16 - 16 (1 bit)

GPOL : Generation Polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of Request
bits : 19 - 23 (5 bit)


RG3CR

DMA Request Generator 3 Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RG3CR RG3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIG_ID OIE GE GPOL GNBREQ

SIG_ID : Signal ID
bits : 0 - 4 (5 bit)

OIE : Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

GE : Generation Enable
bits : 16 - 16 (1 bit)

GPOL : Generation Polarity
bits : 17 - 18 (2 bit)

GNBREQ : Number of Request
bits : 19 - 23 (5 bit)


C14CR

DMA Multiplexer Channel 10 Control register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C14CR C14CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C15CR

DMA Multiplexer Channel 10 Control register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C15CR C15CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA request identification
bits : 0 - 6 (7 bit)

SOIE : Synchronization overrun interrupt enable
bits : 8 - 8 (1 bit)

EGE : Event generation enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Synchronization polarity
bits : 17 - 18 (2 bit)

NBREQ : Number of DMA requests minus 1 to forward
bits : 19 - 23 (5 bit)

SYNC_ID : Synchronization identification
bits : 24 - 28 (5 bit)


C5CR

DMA Multiplexer Channel 5 Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C5CR C5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID OIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

OIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


RGSR

DMA Request Generator Status Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RGSR RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF0 OF1 OF2 OF3

OF0 : Generator Overrun Flag 0
bits : 0 - 0 (1 bit)

OF1 : Generator Overrun Flag 1
bits : 1 - 1 (1 bit)

OF2 : Generator Overrun Flag 2
bits : 2 - 2 (1 bit)

OF3 : Generator Overrun Flag 3
bits : 3 - 3 (1 bit)


RGCFR

DMA Request Generator Clear Flag Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGCFR RGCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF0 CSOF1 CSOF2 CSOF3

CSOF0 : Generator Clear Overrun Flag 0
bits : 0 - 0 (1 bit)

CSOF1 : Generator Clear Overrun Flag 1
bits : 1 - 1 (1 bit)

CSOF2 : Generator Clear Overrun Flag 2
bits : 2 - 2 (1 bit)

CSOF3 : Generator Clear Overrun Flag 3
bits : 3 - 3 (1 bit)


C6CR

DMA Multiplexer Channel 6 Control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C6CR C6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C7CR

DMA Multiplexer Channel 7 Control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C7CR C7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C8CR

DMA Multiplexer Channel 8 Control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C8CR C8CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C9CR

DMA Multiplexer Channel 9 Control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C9CR C9CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C10CR

DMA Multiplexer Channel 10 Control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C10CR C10CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C11CR

DMA Multiplexer Channel 11 Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C11CR C11CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C12CR

DMA Multiplexer Channel 12 Control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C12CR C12CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C13CR

DMA Multiplexer Channel 13 Control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C13CR C13CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C1CR

DMA Multiplexer Channel 1 Control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1CR C1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


C2CR

DMA Multiplexer Channel 2 Control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2CR C2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)


CSR

DMA Multiplexer Channel Status register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF0 SOF1 SOF2 SOF3 SOF4 SOF5 SOF6 SOF7 SOF8 SOF9 SOF10 SOF11 SOF12 SOF13 SOF14 SOF15

SOF0 : Synchronization Overrun Flag 0
bits : 0 - 0 (1 bit)

SOF1 : Synchronization Overrun Flag 1
bits : 1 - 1 (1 bit)

SOF2 : Synchronization Overrun Flag 2
bits : 2 - 2 (1 bit)

SOF3 : Synchronization Overrun Flag 3
bits : 3 - 3 (1 bit)

SOF4 : Synchronization Overrun Flag 4
bits : 4 - 4 (1 bit)

SOF5 : Synchronization Overrun Flag 5
bits : 5 - 5 (1 bit)

SOF6 : Synchronization Overrun Flag 6
bits : 6 - 6 (1 bit)

SOF7 : Synchronization Overrun Flag 7
bits : 7 - 7 (1 bit)

SOF8 : Synchronization Overrun Flag 8
bits : 8 - 8 (1 bit)

SOF9 : Synchronization Overrun Flag 9
bits : 9 - 9 (1 bit)

SOF10 : Synchronization Overrun Flag 10
bits : 10 - 10 (1 bit)

SOF11 : Synchronization Overrun Flag 11
bits : 11 - 11 (1 bit)

SOF12 : Synchronization Overrun Flag 12
bits : 12 - 12 (1 bit)

SOF13 : Synchronization Overrun Flag 13
bits : 13 - 13 (1 bit)

SOF14 : Synchronization Overrun Flag 13
bits : 14 - 14 (1 bit)

SOF15 : Synchronization Overrun Flag 13
bits : 15 - 15 (1 bit)


CCFR

DMA Channel Clear Flag Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCFR CCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOF0 CSOF1 CSOF2 CSOF3 CSOF4 CSOF5 CSOF6 CSOF7 CSOF8 CSOF9 CSOF10 CSOF11 CSOF12 CSOF13 CSOF14 CSOF15

CSOF0 : Synchronization Clear Overrun Flag 0
bits : 0 - 0 (1 bit)

CSOF1 : Synchronization Clear Overrun Flag 1
bits : 1 - 1 (1 bit)

CSOF2 : Synchronization Clear Overrun Flag 2
bits : 2 - 2 (1 bit)

CSOF3 : Synchronization Clear Overrun Flag 3
bits : 3 - 3 (1 bit)

CSOF4 : Synchronization Clear Overrun Flag 4
bits : 4 - 4 (1 bit)

CSOF5 : Synchronization Clear Overrun Flag 5
bits : 5 - 5 (1 bit)

CSOF6 : Synchronization Clear Overrun Flag 6
bits : 6 - 6 (1 bit)

CSOF7 : Synchronization Clear Overrun Flag 7
bits : 7 - 7 (1 bit)

CSOF8 : Synchronization Clear Overrun Flag 8
bits : 8 - 8 (1 bit)

CSOF9 : Synchronization Clear Overrun Flag 9
bits : 9 - 9 (1 bit)

CSOF10 : Synchronization Clear Overrun Flag 10
bits : 10 - 10 (1 bit)

CSOF11 : Synchronization Clear Overrun Flag 11
bits : 11 - 11 (1 bit)

CSOF12 : Synchronization Clear Overrun Flag 12
bits : 12 - 12 (1 bit)

CSOF13 : Synchronization Clear Overrun Flag 13
bits : 13 - 13 (1 bit)

CSOF14 : Synchronization Clear Overrun Flag 13
bits : 14 - 14 (1 bit)

CSOF15 : Synchronization Clear Overrun Flag 13
bits : 15 - 15 (1 bit)


C3CR

DMA Multiplexer Channel 3 Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C3CR C3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAREQ_ID SOIE EGE SE SPOL NBREQ SYNC_ID

DMAREQ_ID : DMA Request ID
bits : 0 - 6 (7 bit)

SOIE : Synchronization Overrun Interrupt Enable
bits : 8 - 8 (1 bit)

EGE : Event Generation Enable
bits : 9 - 9 (1 bit)

SE : Synchronization enable
bits : 16 - 16 (1 bit)

SPOL : Sync polarity
bits : 17 - 18 (2 bit)

NBREQ : Nb request
bits : 19 - 23 (5 bit)

SYNC_ID : SYNC_ID
bits : 24 - 28 (5 bit)



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