Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Memory Remap control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAP : Select the location of the vector table :.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ROM0
Vector Table in ROM.
0x1 : RAM1
Vector Table in RAM.
0x2 : FLASH0
Vector Table in Flash.
0x3 : FLASH1
Vector Table in Flash.
End of enumeration elements list.
AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_CPU0_CBUS : CPU0 C-AHB bus.
bits : 0 - 1 (2 bit)
access : read-write
PRI_CPU0_SBUS : CPU0 S-AHB bus.
bits : 2 - 3 (2 bit)
access : read-write
PRI_CPU1_CBUS : CPU1 C-AHB bus.
bits : 4 - 5 (2 bit)
access : read-write
PRI_CPU1_SBUS : CPU1 S-AHB bus.
bits : 6 - 7 (2 bit)
access : read-write
PRI_USB_FS : USB-FS.(USB0)
bits : 8 - 9 (2 bit)
access : read-write
PRI_SDMA0 : DMA0 controller priority.
bits : 10 - 11 (2 bit)
access : read-write
PRI_SDIO : SDIO.
bits : 16 - 17 (2 bit)
access : read-write
PRI_PQ : PQ (HW Accelerator).
bits : 18 - 19 (2 bit)
access : read-write
PRI_HASH_AES : HASH_AES.
bits : 20 - 21 (2 bit)
access : read-write
PRI_USB_HS : USB-HS.(USB1)
bits : 22 - 23 (2 bit)
access : read-write
PRI_SDMA1 : DMA1 controller priority.
bits : 24 - 25 (2 bit)
access : read-write
Peripheral reset control 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
ROM_RST : ROM reset control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SRAM_CTRL1_RST : SRAM Controller 1 reset control.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SRAM_CTRL2_RST : SRAM Controller 2 reset control.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SRAM_CTRL3_RST : SRAM Controller 3 reset control.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SRAM_CTRL4_RST : SRAM Controller 4 reset control.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FLASH_RST : Flash controller reset control.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FMC_RST : FMC controller reset control.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
MUX_RST : Input Mux reset control.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
IOCON_RST : I/O controller reset control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO0_RST : GPIO0 reset control.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO1_RST : GPIO1 reset control.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO2_RST : GPIO2 reset control.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO3_RST : GPIO3 reset control.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
PINT_RST : Pin interrupt (PINT) reset control.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GINT_RST : Group interrupt (GINT) reset control.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
DMA0_RST : DMA0 reset control.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
CRCGEN_RST : CRCGEN reset control.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
WWDT_RST : Watchdog Timer reset control.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
RTC_RST : Real Time Clock (RTC) reset control.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
MAILBOX_RST : Inter CPU communication Mailbox reset control.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
ADC_RST : ADC reset control.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
MRT_RST : MRT reset control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
OSTIMER_RST : OS Event Timer reset control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SCT_RST : SCT reset control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SCTIPU_RST : SCTIPU reset control.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
UTICK_RST : UTICK reset control.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC0_RST : FC0 reset control.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC1_RST : FC1 reset control.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC2_RST : FC2 reset control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC3_RST : FC3 reset control.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC4_RST : FC4 reset control.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC5_RST : FC5 reset control.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC6_RST : FC6 reset control.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FC7_RST : FC7 reset control.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
TIMER2_RST : Timer 2 reset control.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB0_DEV_RST : USB0 DEV reset control.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
TIMER0_RST : Timer 0 reset control.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
TIMER1_RST : Timer 1 reset control.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
DMA1_RST : DMA1 reset control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
COMP_RST : Comparator reset control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SDIO_RST : SDIO reset control.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB1_HOST_RST : USB1 Host reset control.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB1_DEV_RST : USB1 dev reset control.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB1_RAM_RST : USB1 RAM reset control.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB1_PHY_RST : USB1 PHY reset control.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
FREQME_RST : Frequency meter reset control.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
RNG_RST : RNG reset control.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
SYSCTL_RST : SYSCTL Block reset.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB0_HOSTM_RST : USB0 Host Master reset control.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
USB0_HOSTS_RST : USB0 Host Slave reset control.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
HASH_AES_RST : HASH_AES reset control.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
PQ_RST : Power Quad reset control.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
PLULUT_RST : PLU LUT reset control.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
TIMER3_RST : Timer 3 reset control.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
TIMER4_RST : Timer 4 reset control.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
PUF_RST : PUF reset control reset control.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
CASPER_RST : Casper reset control.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
ANALOG_CTRL_RST : analog control reset control.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
HS_LSPI_RST : HS LSPI reset control.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO_SEC_RST : GPIO secure reset control.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
GPIO_SEC_INT_RST : GPIO secure int reset control.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
Bloc is not reset.
0x1 : ASSERTED
Bloc is reset.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PRESETCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
generate a software_reset
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWR_RESET : Write 0x5A00_0001 to generate a software_reset.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration:
0 : RELEASED
Bloc is not reset.
0x5A000001 : ASSERTED
Generate a software reset.
End of enumeration elements list.
AHB Clock control 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
ROM : Enables the clock for the ROM.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SRAM_CTRL1 : Enables the clock for the SRAM Controller 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SRAM_CTRL2 : Enables the clock for the SRAM Controller 2.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SRAM_CTRL3 : Enables the clock for the SRAM Controller 3.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SRAM_CTRL4 : Enables the clock for the SRAM Controller 4.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FLASH : Enables the clock for the Flash controller.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FMC : Enables the clock for the FMC controller.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
MUX : Enables the clock for the Input Mux.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
IOCON : Enables the clock for the I/O controller.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO0 : Enables the clock for the GPIO0.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO1 : Enables the clock for the GPIO1.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO2 : Enables the clock for the GPIO2.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO3 : Enables the clock for the GPIO3.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
PINT : Enables the clock for the Pin interrupt (PINT).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GINT : Enables the clock for the Group interrupt (GINT).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
DMA0 : Enables the clock for the DMA0.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
CRCGEN : Enables the clock for the CRCGEN.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
WWDT : Enables the clock for the Watchdog Timer.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
RTC : Enables the clock for the Real Time Clock (RTC).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
MAILBOX : Enables the clock for the Inter CPU communication Mailbox.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
ADC : Enables the clock for the ADC.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
AHB Clock control 1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
MRT : Enables the clock for the MRT.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
OSTIMER : Enables the clock for the OS Event Timer.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SCT : Enables the clock for the SCT.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
UTICK : Enables the clock for the UTICK.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC0 : Enables the clock for the FC0.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC1 : Enables the clock for the FC1.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC2 : Enables the clock for the FC2.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC3 : Enables the clock for the FC3.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC4 : Enables the clock for the FC4.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC5 : Enables the clock for the FC5.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC6 : Enables the clock for the FC6.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FC7 : Enables the clock for the FC7.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
TIMER2 : Enables the clock for the Timer 2.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB0_DEV : Enables the clock for the USB0 DEV.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
TIMER0 : Enables the clock for the Timer 0.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
TIMER1 : Enables the clock for the Timer 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
AHB Clock control 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
DMA1 : Enables the clock for the DMA1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
COMP : Enables the clock for the Comparator.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SDIO : Enables the clock for the SDIO.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB1_HOST : Enables the clock for the USB1 Host.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB1_DEV : Enables the clock for the USB1 dev.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB1_RAM : Enables the clock for the USB1 RAM.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB1_PHY : Enables the clock for the USB1 PHY.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
FREQME : Enables the clock for the Frequency meter.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
RNG : Enables the clock for the RNG.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
SYSCTL : SYSCTL block clock.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB0_HOSTM : Enables the clock for the USB0 Host Master.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
USB0_HOSTS : Enables the clock for the USB0 Host Slave.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
HASH_AES : Enables the clock for the HASH_AES.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
PQ : Enables the clock for the Power Quad.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
PLULUT : Enables the clock for the PLU LUT.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
TIMER3 : Enables the clock for the Timer 3.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
TIMER4 : Enables the clock for the Timer 4.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
PUF : Enables the clock for the PUF reset control.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
CASPER : Enables the clock for the Casper.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
ANALOG_CTRL : Enables the clock for the analog control.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
HS_LSPI : Enables the clock for the HS LSPI.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO_SEC : Enables the clock for the GPIO secure.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
GPIO_SEC_INT : Enables the clock for the GPIO secure int.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Clock.
0x1 : ENABLE
Enable Clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : AHBCLKCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control set register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
System Tick Timer for CPU0 source select
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SYSTICKCLKSEL
reset_Mask : 0x0
SEL : System Tick Timer for CPU0 source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
System Tick 0 divided clock.
0x1 : ENUM_0x1
FRO 1MHz clock.
0x2 : ENUM_0x2
Oscillator 32 kHz clock.
0x3 : ENUM_0x3
No clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SYSTICKCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
System Tick Timer for CPU1 source select
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SYSTICKCLKSEL
reset_Mask : 0x0
SEL : System Tick Timer for CPU1 source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
System Tick 1 divided clock.
0x1 : ENUM_0x1
FRO 1MHz clock.
0x2 : ENUM_0x2
Oscillator 32 kHz clock.
0x3 : ENUM_0x3
No clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SYSTICKCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Trace clock source select
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Trace clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Trace divided clock.
0x1 : ENUM_0x1
FRO 1MHz clock.
0x2 : ENUM_0x2
Oscillator 32 kHz clock.
0x3 : ENUM_0x3
No clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
CTimer 0 clock source select
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
SEL : CTimer 0 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
CTimer 1 clock source select
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
SEL : CTimer 1 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
CTimer 2 clock source select
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
SEL : CTimer 2 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
CTimer 3 clock source select
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
SEL : CTimer 3 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
CTimer 4 clock source select
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
SEL : CTimer 4 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CTIMERCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control clear register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Main clock A source select
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Main clock A source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
FRO 12 MHz clock.
0x1 : ENUM_0x1
CLKIN clock.
0x2 : ENUM_0x2
FRO 1MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
End of enumeration elements list.
Main clock source select
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : Main clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main Clock A.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
PLL1 clock.
0x3 : ENUM_0x3
Oscillator 32 kHz clock.
End of enumeration elements list.
CLKOUT clock source select
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : CLKOUT clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
CLKIN clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
PLL1 clock.
0x6 : ENUM_0x6
Oscillator 32kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
PLL0 clock source select
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : PLL0 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
FRO 12 MHz clock.
0x1 : ENUM_0x1
CLKIN clock.
0x2 : ENUM_0x2
FRO 1MHz clock.
0x3 : ENUM_0x3
Oscillator 32kHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
PLL1 clock source select
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : PLL1 clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
FRO 12 MHz clock.
0x1 : ENUM_0x1
CLKIN clock.
0x2 : ENUM_0x2
FRO 1MHz clock.
0x3 : ENUM_0x3
Oscillator 32kHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
ADC clock source select
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : ADC clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
FRO 96 MHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
FS USB clock source select
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : FS USB clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
PLL1 clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Flexcomm Interface 0 clock source select for Fractional Rate Divider
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 0 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 1 clock source select for Fractional Rate Divider
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 1 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 2 clock source select for Fractional Rate Divider
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 2 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 3 clock source select for Fractional Rate Divider
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 3 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 4 clock source select for Fractional Rate Divider
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 4 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 5 clock source select for Fractional Rate Divider
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 5 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 6 clock source select for Fractional Rate Divider
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 6 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Flexcomm Interface 7 clock source select for Fractional Rate Divider
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
SEL : Flexcomm Interface 7 clock source select for Fractional Rate Divider.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FCCLKSEL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
HS LSPI clock source select
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : HS LSPI clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
system PLL divided clock.
0x2 : ENUM_0x2
FRO 12 MHz clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
FRO 1MHz clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
Oscillator 32 kHz clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
MCLK clock source select
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : MCLK clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
FRO 96 MHz clock.
0x1 : ENUM_0x1
PLL0 clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
No clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
SCTimer/PWM clock source select
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SCTimer/PWM clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
CLKIN clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
MCLK clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
SDIO clock source select
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SDIO clock source select.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : ENUM_0x0
Main clock.
0x1 : ENUM_0x1
PLL0 clock.
0x2 : ENUM_0x2
No clock.
0x3 : ENUM_0x3
FRO 96 MHz clock.
0x4 : ENUM_0x4
No clock.
0x5 : ENUM_0x5
PLL1 clock.
0x6 : ENUM_0x6
No clock.
0x7 : ENUM_0x7
No clock.
End of enumeration elements list.
System Tick Timer divider for CPU0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
System Tick Timer divider for CPU1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
TRACE clock divider
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
Fractional rate divider for flexcomm 0
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 1
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 2
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 3
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 4
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 5
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 6
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Fractional rate divider for flexcomm 7
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DIV : Denominator of the fractional rate divider.
bits : 0 - 7 (8 bit)
access : read-write
MULT : Numerator of the fractional rate divider.
bits : 8 - 15 (8 bit)
access : read-write
Peripheral reset control register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FLEXFRGCTRL
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control set register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
System tick calibration for secure part of CPU0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-write
SKEW : Initial value for the Systick timer.
bits : 24 - 24 (1 bit)
access : read-write
NOREF : Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided.
bits : 25 - 25 (1 bit)
access : read-write
System clock divider
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
CLKOUT clock divider
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
FRO_HF (96MHz) clock divider
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
WDT clock divider
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 5 (6 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
ADC clock divider
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 2 (3 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
USB0 Clock divider
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
I2S MCLK clock divider
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
SCT/PWM clock divider
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
SDIO clock divider
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
System tick calibration for non-secure part of CPU0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-write
SKEW : Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
bits : 24 - 24 (1 bit)
access : read-write
NOREF : Initial value for the Systick timer.
bits : 25 - 25 (1 bit)
access : read-write
Peripheral reset control clear register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
PLL0 clock divider
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Clock divider value.
bits : 0 - 7 (8 bit)
access : read-write
RESET : Resets the divider counter.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
0 : RELEASED
Divider is not reset.
0x1 : ASSERTED
Divider is reset.
End of enumeration elements list.
HALT : Halts the divider counter.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : RUN
Divider clock is running.
0x1 : HALT
Divider clock is stoped.
End of enumeration elements list.
REQFLAG : Divider status flag.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : STABLE
Divider clock is stable.
0x1 : ONGOING
Clock frequency is not stable.
End of enumeration elements list.
Control clock configuration registers access (like xxxDIV, xxxSEL)
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLOCKGENUPDATELOCKOUT : Control clock configuration registers access (like xxxDIV, xxxSEL).
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : FREEZE
all hardware clock configruration are freeze.
0x1 : ENABLE
update all clock configuration.
End of enumeration elements list.
System tick calibration for CPU1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-write
SKEW : Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
bits : 24 - 24 (1 bit)
access : read-write
NOREF : Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided.
bits : 25 - 25 (1 bit)
access : read-write
FMC configuration register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHTIM : Flash memory access time.
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : FLASHTIM0
1 system clock flash access time (for system clock rates up to 11 MHz).
0x1 : FLASHTIM1
2 system clocks flash access time (for system clock rates up to 22 MHz).
0x2 : FLASHTIM2
3 system clocks flash access time (for system clock rates up to 33 MHz).
0x3 : FLASHTIM3
4 system clocks flash access time (for system clock rates up to 44 MHz).
0x4 : FLASHTIM4
5 system clocks flash access time (for system clock rates up to 55 MHz).
0x5 : FLASHTIM5
6 system clocks flash access time (for system clock rates up to 66 MHz).
0x6 : FLASHTIM6
7 system clocks flash access time (for system clock rates up to 77 MHz).
0x7 : FLASHTIM7
8 system clocks flash access time (for system clock rates up to 88 MHz).
0x8 : FLASHTIM8
9 system clocks flash access time (for system clock rates up to 100 MHz).
End of enumeration elements list.
USB0 need clock control
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AP_FS_DEV_NEEDCLK : USB0 Device USB0_NEEDCLK signal control:.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HW_CTRL
Under hardware control.
0x1 : FORCED
Forced high.
End of enumeration elements list.
POL_FS_DEV_NEEDCLK : USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FALLING
Falling edge of device USB0_NEEDCLK triggers wake-up.
0x1 : RISING
Rising edge of device USB0_NEEDCLK triggers wake-up.
End of enumeration elements list.
AP_FS_HOST_NEEDCLK : USB0 Host USB0_NEEDCLK signal control:.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HW_CTRL
Under hardware control.
0x1 : FORCED
Forced high.
End of enumeration elements list.
POL_FS_HOST_NEEDCLK : USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FALLING
Falling edge of device USB0_NEEDCLK triggers wake-up.
0x1 : RISING
Rising edge of device USB0_NEEDCLK triggers wake-up.
End of enumeration elements list.
USB0 need clock status
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_NEEDCLK : USB0 Device USB0_NEEDCLK signal status:.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : LOW
USB0 Device clock is low.
0x1 : HIGH
USB0 Device clock is high.
End of enumeration elements list.
HOST_NEEDCLK : USB0 Host USB0_NEEDCLK signal status:.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : LOW
USB0 Host clock is low.
0x1 : HIGH
USB0 Host clock is high.
End of enumeration elements list.
FMCflush control
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FLUSH : Flush control
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : NO_FLUSH
No action is performed.
0x1 : FLUSH
Flush the FMC buffer contents.
End of enumeration elements list.
MCLK control
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKIO : MCLK control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INPUT
input mode.
0x1 : OUTPUT
output mode.
End of enumeration elements list.
USB1 need clock control
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AP_HS_DEV_NEEDCLK : USB1 Device need_clock signal control:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HW_CTRL
HOST_NEEDCLK is under hardware control.
0x1 : FORCED
HOST_NEEDCLK is forced high.
End of enumeration elements list.
POL_HS_DEV_NEEDCLK : USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FALLING
Falling edge of DEV_NEEDCLK triggers wake-up.
0x1 : RISING
Rising edge of DEV_NEEDCLK triggers wake-up.
End of enumeration elements list.
AP_HS_HOST_NEEDCLK : USB1 Host need clock signal control:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : HW_CTRL
HOST_NEEDCLK is under hardware control.
0x1 : FORCED
HOST_NEEDCLK is forced high.
End of enumeration elements list.
POL_HS_HOST_NEEDCLK : USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FALLING
Falling edge of HOST_NEEDCLK triggers wake-up.
0x1 : RISING
Rising edge of HOST_NEEDCLK triggers wake-up.
End of enumeration elements list.
HS_DEV_WAKEUP_N : Software override of device controller PHY wake up logic.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : FORCE_WUP
Forces USB1_PHY to wake-up.
0x1 : NORMAL_WUP
Normal USB1_PHY behavior.
End of enumeration elements list.
USB1 need clock status
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEV_NEEDCLK : USB1 Device need_clock signal status:.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : LOW
DEV_NEEDCLK is low.
0x1 : HIGH
DEV_NEEDCLK is high.
End of enumeration elements list.
HOST_NEEDCLK : USB1 Host need_clock signal status:.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : LOW
HOST_NEEDCLK is low.
0x1 : HIGH
HOST_NEEDCLK is high.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
SDIO CCLKIN phase and delay control
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCLK_DRV_PHASE : Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_0_DEG
0 degree shift.
0x1 : ENUM_90_DEG
90 degree shift.
0x2 : ENUM_180_DEG
180 degree shift.
0x3 : ENUM_270_DEG
270 degree shift.
End of enumeration elements list.
CCLK_SAMPLE_PHASE : Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : ENUM_0_DEG
0 degree shift.
0x1 : ENUM_90_DEG
90 degree shift.
0x2 : ENUM_180_DEG
180 degree shift.
0x3 : ENUM_270_DEG
270 degree shift.
End of enumeration elements list.
PHASE_ACTIVE : Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : BYPASSED
Bypassed.
0x1 : PH_SHIFT
Activates phase shift logic. When active, the clock divider is active and phase delays are enabled.
End of enumeration elements list.
CCLK_DRV_DELAY : Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
bits : 16 - 20 (5 bit)
access : read-write
CCLK_DRV_DELAY_ACTIVE : Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable drive delay.
0x1 : ENABLE
Enable drive delay.
End of enumeration elements list.
CCLK_SAMPLE_DELAY : Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
bits : 24 - 28 (5 bit)
access : read-write
CCLK_SAMPLE_DELAY_ACTIVE : Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disables sample delay.
0x1 : ENABLE
Enables sample delay.
End of enumeration elements list.
NMI Source Select
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQCPU0 : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0.
bits : 0 - 5 (6 bit)
access : read-write
IRQCPU1 : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1.
bits : 8 - 13 (6 bit)
access : read-write
NMIENCPU1 : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1.
bits : 30 - 30 (1 bit)
access : read-write
NMIENCPU0 : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
bits : 31 - 31 (1 bit)
access : read-write
Peripheral reset control register
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control set register
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control clear register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
PLL1 550m control
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELR : Bandwidth select R value.
bits : 0 - 3 (4 bit)
access : read-write
SELI : Bandwidth select I value.
bits : 4 - 9 (6 bit)
access : read-write
SELP : Bandwidth select P value.
bits : 10 - 14 (5 bit)
access : read-write
BYPASSPLL : Bypass PLL input clock is sent directly to the PLL output (default).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : USED
use PLL.
0x1 : BYPASSED
PLL input clock is sent directly to the PLL output.
End of enumeration elements list.
BYPASSPOSTDIV2 : bypass of the divide-by-2 divider in the post-divider.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : USED
use the divide-by-2 divider in the post-divider.
0x1 : BYPASSED
bypass of the divide-by-2 divider in the post-divider.
End of enumeration elements list.
LIMUPOFF : limup_off = 1 in spread spectrum and fractional PLL applications.
bits : 17 - 17 (1 bit)
access : read-write
BWDIRECT : control of the bandwidth of the PLL.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SYNC
the bandwidth is changed synchronously with the feedback-divider.
0x1 : DIRECT
modify the bandwidth of the PLL directly.
End of enumeration elements list.
BYPASSPREDIV : bypass of the pre-divider.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : USED
use the pre-divider.
0x1 : BYPASSED
bypass of the pre-divider.
End of enumeration elements list.
BYPASSPOSTDIV : bypass of the post-divider.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : USED
use the post-divider.
0x1 : BYPASSED
bypass of the post-divider.
End of enumeration elements list.
CLKEN : enable the output clock.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable the output clock.
0x1 : ENABLE
Enable the output clock.
End of enumeration elements list.
FRMEN : 1: free running mode.
bits : 22 - 22 (1 bit)
access : read-write
FRMCLKSTABLE : free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
bits : 23 - 23 (1 bit)
access : read-write
SKEWEN : Skew mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
skewmode is disable.
0x1 : ENABLE
skewmode is enable.
End of enumeration elements list.
PLL1 550m status
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
bits : 0 - 0 (1 bit)
access : read-only
PREDIVACK : pre-divider ratio change acknowledge.
bits : 1 - 1 (1 bit)
access : read-only
FEEDDIVACK : feedback divider ratio change acknowledge.
bits : 2 - 2 (1 bit)
access : read-only
POSTDIVACK : post-divider ratio change acknowledge.
bits : 3 - 3 (1 bit)
access : read-only
FRMDET : free running detector output (active high).
bits : 4 - 4 (1 bit)
access : read-only
PLL1 550m N divider
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDIV : pre-divider divider ratio (N-divider).
bits : 0 - 7 (8 bit)
access : read-write
NREQ : pre-divider ratio change request.
bits : 8 - 8 (1 bit)
access : read-write
PLL1 550m M divider
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDIV : feedback divider divider ratio (M-divider).
bits : 0 - 15 (16 bit)
access : read-write
MREQ : feedback ratio change request.
bits : 16 - 16 (1 bit)
access : read-write
PLL1 550m P divider
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIV : post-divider divider ratio (P-divider)
bits : 0 - 4 (5 bit)
access : read-write
PREQ : feedback ratio change request.
bits : 5 - 5 (1 bit)
access : read-write
PLL0 550m control
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELR : Bandwidth select R value.
bits : 0 - 3 (4 bit)
access : read-write
SELI : Bandwidth select I value.
bits : 4 - 9 (6 bit)
access : read-write
SELP : Bandwidth select P value.
bits : 10 - 14 (5 bit)
access : read-write
BYPASSPLL : Bypass PLL input clock is sent directly to the PLL output (default).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : USED
use PLL.
0x1 : BYPASSED
Bypass PLL input clock is sent directly to the PLL output.
End of enumeration elements list.
BYPASSPOSTDIV2 : bypass of the divide-by-2 divider in the post-divider.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : USED
use the divide-by-2 divider in the post-divider.
0x1 : BYPASSED
bypass of the divide-by-2 divider in the post-divider.
End of enumeration elements list.
LIMUPOFF : limup_off = 1 in spread spectrum and fractional PLL applications.
bits : 17 - 17 (1 bit)
access : read-write
BWDIRECT : Control of the bandwidth of the PLL.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SYNC
the bandwidth is changed synchronously with the feedback-divider.
0x1 : DIRECT
modify the bandwidth of the PLL directly.
End of enumeration elements list.
BYPASSPREDIV : bypass of the pre-divider.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : USED
use the pre-divider.
0x1 : BYPASSED
bypass of the pre-divider.
End of enumeration elements list.
BYPASSPOSTDIV : bypass of the post-divider.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : USED
use the post-divider.
0x1 : BYPASSED
bypass of the post-divider.
End of enumeration elements list.
CLKEN : enable the output clock.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
disable the output clock.
0x1 : ENABLE
enable the output clock.
End of enumeration elements list.
FRMEN : free running mode.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
free running mode is disable.
0x1 : ENABLE
free running mode is enable.
End of enumeration elements list.
FRMCLKSTABLE : free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.
bits : 23 - 23 (1 bit)
access : read-write
SKEWEN : skew mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
skew mode is disable.
0x1 : ENABLE
skew mode is enable.
End of enumeration elements list.
PLL0 550m status
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
bits : 0 - 0 (1 bit)
access : read-only
PREDIVACK : pre-divider ratio change acknowledge.
bits : 1 - 1 (1 bit)
access : read-only
FEEDDIVACK : feedback divider ratio change acknowledge.
bits : 2 - 2 (1 bit)
access : read-only
POSTDIVACK : post-divider ratio change acknowledge.
bits : 3 - 3 (1 bit)
access : read-only
FRMDET : free running detector output (active high).
bits : 4 - 4 (1 bit)
access : read-only
PLL0 550m N divider
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDIV : pre-divider divider ratio (N-divider).
bits : 0 - 7 (8 bit)
access : read-write
NREQ : pre-divider ratio change request.
bits : 8 - 8 (1 bit)
access : read-write
PLL0 550m P divider
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDIV : post-divider divider ratio (P-divider)
bits : 0 - 4 (5 bit)
access : read-write
PREQ : feedback ratio change request.
bits : 5 - 5 (1 bit)
access : read-write
PLL0 Spread Spectrum Wrapper control register 0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD_LBS : input word of the wrapper bit 31 to 0.
bits : 0 - 31 (32 bit)
access : read-write
PLL0 Spread Spectrum Wrapper control register 1
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD_MBS : input word of the wrapper bit 32.
bits : 0 - 0 (1 bit)
access : read-write
MD_REQ : md change request.
bits : 1 - 1 (1 bit)
access : read-write
MF : programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.
bits : 2 - 4 (3 bit)
access : read-write
MR : programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1.
bits : 5 - 7 (3 bit)
access : read-write
MC : modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.
bits : 8 - 9 (2 bit)
access : read-write
MDIV_EXT : to select an external mdiv value.
bits : 10 - 25 (16 bit)
access : read-write
MREQ : to select an external mreq value.
bits : 26 - 26 (1 bit)
access : read-write
DITHER : dithering between two modulation frequencies in a random way or in a pseudo random way (white noise), in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen.
bits : 27 - 27 (1 bit)
access : read-write
SEL_EXT : to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext.
bits : 28 - 28 (1 bit)
access : read-write
Peripheral reset control register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
CPU Control for multiple processors
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1CLKEN : CPU1 clock enable.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The CPU1 clock is not enabled.
0x1 : ENABLE
The CPU1 clock is enabled.
End of enumeration elements list.
CPU1RSTEN : CPU1 reset.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : RELEASED
The CPU1 is not being reset.
0x1 : ASSERTED
The CPU1 is being reset.
End of enumeration elements list.
Coprocessor Boot Address
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPBOOT : Coprocessor Boot Address for CPU1.
bits : 0 - 31 (32 bit)
access : read-write
CPU Status
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0SLEEPING : The CPU0 sleeping state.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : AWAKE
the CPU is not sleeping.
0x1 : SLEEPING
the CPU is sleeping.
End of enumeration elements list.
CPU1SLEEPING : The CPU1 sleeping state.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : AWAKE
the CPU is not sleeping.
0x1 : SLEEPING
the CPU is sleeping.
End of enumeration elements list.
CPU0LOCKUP : The CPU0 lockup state.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : AWAKE
the CPU is not in lockup.
0x1 : SLEEPING
the CPU is in lockup.
End of enumeration elements list.
CPU1LOCKUP : The CPU1 lockup state.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : AWAKE
the CPU is not in lockup.
0x1 : SLEEPING
the CPU is in lockup.
End of enumeration elements list.
Peripheral reset control register
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Peripheral reset control register
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data array value
bits : 0 - 31 (32 bit)
access : read-write
Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL32MHZ_FREQM_ENA : Enable XTAL32MHz clock for Frequency Measure module.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
FRO1MHZ_UTICK_ENA : Enable FRO 1MHz clock for Frequency Measure module and for UTICK.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
FRO12MHZ_FREQM_ENA : Enable FRO 12MHz clock for Frequency Measure module.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
FRO_HF_FREQM_ENA : Enable FRO 96MHz clock for Frequency Measure module.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
CLKIN_ENA : Enable clock_in clock for clock module.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
FRO1MHZ_CLK_ENA : Enable FRO 1MHz clock for clock muxing in clock gen.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
ANA_FRO12M_CLK_ENA : Enable FRO 12MHz clock for analog control of the FRO 192MHz.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
XO_CAL_CLK_ENA : Enable clock for cristal oscilator calibration.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
PLU_DEGLITCH_CLK_ENA : Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The clock is not enabled.
0x1 : ENABLE
The clock is enabled.
End of enumeration elements list.
Comparator Interrupt control
address_offset : 0xB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_ENABLE : Analog Comparator interrupt enable control:.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INT_DISABLE
interrupt disable.
0x1 : INT_ENABLE
interrupt enable.
End of enumeration elements list.
INT_CLEAR : Analog Comparator interrupt clear.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NONE
No effect.
0x1 : CLEAR
Clear the interrupt. Self-cleared bit.
End of enumeration elements list.
INT_CTRL : Comparator interrupt type selector:.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : EDGE_DISABLE
The analog comparator interrupt edge sensitive is disabled.
0x1 : LVL_DISABLE
The analog comparator interrupt level sensitive is disabled.
0x2 : EDGE_RISING
analog comparator interrupt is rising edge sensitive.
0x3 : LVL_HIGH
Analog Comparator interrupt is high level sensitive.
0x4 : EDGE_FALLING
analog comparator interrupt is falling edge sensitive.
0x5 : LVL_LOW
Analog Comparator interrupt is low level sensitive.
0x6 : EDGE_BOTH
analog comparator interrupt is rising and falling edge sensitive.
0x7 : LVL_DIS2
The analog comparator interrupt level sensitive is disabled.
End of enumeration elements list.
INT_SOURCE : Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : FILTER_INT
Select Analog Comparator filtered output as input for interrupt detection.
0x1 : RAW_INT
Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode.
End of enumeration elements list.
Comparator Interrupt status
address_offset : 0xB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATUS : Interrupt status BEFORE Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NO_INT
no interrupt pending.
0x1 : PENDING
interrupt pending.
End of enumeration elements list.
INT_STATUS : Interrupt status AFTER Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NO_INT
no interrupt pending.
0x1 : PENDING
interrupt pending.
End of enumeration elements list.
VAL : comparator analog output.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : SMALLER
P+ is smaller than P-.
0x1 : GREATER
P+ is greater than P-.
End of enumeration elements list.
Control automatic clock gating
address_offset : 0xE04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROM : Control automatic clock gating of ROM controller.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAMX_CTRL : Control automatic clock gating of RAMX controller.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAM0_CTRL : Control automatic clock gating of RAM0 controller.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAM1_CTRL : Control automatic clock gating of RAM1 controller.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAM2_CTRL : Control automatic clock gating of RAM2 controller.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAM3_CTRL : Control automatic clock gating of RAM3 controller.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
RAM4_CTRL : Control automatic clock gating of RAM4 controller.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
SYNC0_APB : Control automatic clock gating of synchronous bridge controller 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
SYNC1_APB : Control automatic clock gating of synchronous bridge controller 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
CRCGEN : Control automatic clock gating of CRCGEN controller.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
SDMA0 : Control automatic clock gating of DMA0 controller.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
SDMA1 : Control automatic clock gating of DMA1 controller.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
USB0 : Control automatic clock gating of USB controller.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
SYSCON : Control automatic clock gating of synchronous system controller registers bank.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Automatic clock gating is not overridden.
0x1 : ENABLE
Automatic clock gating is overridden (Clock gating is disabled).
End of enumeration elements list.
ENABLEUPDATE : The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.
bits : 16 - 31 (16 bit)
access : write-only
Enumeration:
0 : DISABLE
Bit Fields 0 - 15 of this register are not updated
0xC0DE : ENABLE
Bit Fields 0 - 15 of this register are updated
End of enumeration elements list.
Enable bypass of the first stage of synchonization inside GPIO_INT module
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSYNC : Enable bypass of the first stage of synchonization inside GPIO_INT module.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : USED
use the first stage of synchonization inside GPIO_INT module.
0x1 : BYPASS
bypass of the first stage of synchonization inside GPIO_INT module.
End of enumeration elements list.
Control write access to security registers.
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_ALL : Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : DISABLE
Any other value than b1010: disable write access to all 6 registers.
0xA : ENABLE
1010: Enable write access to all 6 registers.
End of enumeration elements list.
Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control.
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0_DBGEN : CPU0 Invasive debug control:.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_NIDEN : CPU0 Non Invasive debug control:.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_SPIDEN : CPU0 Secure Invasive debug control:.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_SPNIDEN : CPU0 Secure Non Invasive debug control:.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU1_DBGEN : CPU1 Invasive debug control:.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU1_NIDEN : CPU1 Non Invasive debug control:.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register.
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU0_DBGEN : CPU0 (CPU0) Invasive debug control:.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_NIDEN : CPU0 Non Invasive debug control:.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_SPIDEN : CPU0 Secure Invasive debug control:.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU0_SPNIDEN : CPU0 Secure Non Invasive debug control:.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU1_DBGEN : CPU1 Invasive debug control:.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
CPU1_NIDEN : CPU1 Non Invasive debug control:.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Any other value than b10: invasive debug is disable.
0x2 : ENABLE
10: Invasive debug is enabled.
End of enumeration elements list.
block quiddikey/PUF all index.
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY_BLOCK : Write a value to block quiddikey/PUF all index.
bits : 0 - 31 (32 bit)
access : write-only
Debug authentication BEACON register
address_offset : 0xFC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BEACON : Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code.
bits : 0 - 31 (32 bit)
access : read-write
CPUs configuration register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1ENABLE : Enable CPU1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
CPU1 is disable (Processor in reset).
0x1 : ENABLE
CPU1 is enable.
End of enumeration elements list.
Device ID
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ROM_REV_MINOR : ROM revision.
bits : 20 - 23 (4 bit)
access : read-only
Chip revision ID and Number
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REV_ID : Chip Metal Revision ID.
bits : 0 - 3 (4 bit)
access : read-only
MCO_NUM_IN_DIE_ID : Chip Number 0x426B.
bits : 4 - 23 (20 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.