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SAU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TYPE

RNR

RBAR

RLAR

SFSR

SFAR


CTRL

Security Attribution Unit Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE ALLNS

ENABLE : Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

The SAU is disabled.

0x1 : ENABLED

The SAU is enabled.

End of enumeration elements list.

ALLNS : All Non-secure.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURED_MEMORY

Memory is marked as Secure and is not Non-secure callable.

0x1 : NON_SECURED_MEMORY

Memory is marked as Non-secure.

End of enumeration elements list.


TYPE

Security Attribution Unit Type Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SREGION

SREGION : SAU regions. The number of implemented SAU regions.
bits : 0 - 7 (8 bit)
access : read-write


RNR

Security Attribution Unit Region Number Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNR RNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION

REGION : Region number.
bits : 0 - 7 (8 bit)
access : read-write


RBAR

Security Attribution Unit Region Base Address Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR RBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BADDR

BADDR : Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4:0] of the base address are defined as 0x00.
bits : 5 - 31 (27 bit)
access : read-write


RLAR

Security Attribution Unit Region Limit Address Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RLAR RLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE NSC LADDR

ENABLE : Enable. SAU region enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ENABLED

SAU region is enabled.

0x1 : DISABLED

SAU region is disabled.

End of enumeration elements list.

NSC : Non-secure callable. Controls whether Non-secure state is permitted to execute an SG instruction from this region.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_NON_SECURE_CALLABLE

Region is not Non-secure callable.

0x1 : NON_SECURE_CALLABLE

Region is Non-secure callable.

End of enumeration elements list.

LADDR : Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits[4:0] of the limit address are defined as 0x1F.
bits : 5 - 31 (27 bit)
access : read-write


SFSR

Secure Fault Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFSR SFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVEP INVIS INVER AUVIOL INVTRAN LSPERR SFARVALID LSERR

INVEP : Invalid entry point.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

INVIS : Invalid integrity signature flag.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

INVER : Invalid exception return flag.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

AUVIOL : Attribution unit violation flag.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

INVTRAN : Invalid transition flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

LSPERR : Lazy state preservation error flag.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred.

0x1 : ERROR

Error has occurred.

End of enumeration elements list.

SFARVALID : Secure fault address valid.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_VALID

SFAR content not valid.

0x1 : VALID

SFAR content valid.

End of enumeration elements list.

LSERR : Lazy state error flag.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NO_ERROR

Error has not occurred

0x1 : ERROR

Error has occurred.

End of enumeration elements list.


SFAR

Secure Fault Address Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFAR SFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an access that caused an SAU violation.
bits : 0 - 31 (32 bit)
access : read-write



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