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ICache

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ICACHE_CR

ICACHE_HMONR

ICACHE_MMONR

ICACHE_CRR0

ICACHE_CRR1

ICACHE_CRR2

ICACHE_CRR3

ICACHE_SR

ICACHE_IER

ICACHE_FCR


ICACHE_CR

ICACHE control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_CR ICACHE_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN CACHEINV WAYSEL HITMEN MISSMEN HITMRST MISSMRST

EN : EN
bits : 0 - 0 (1 bit)

CACHEINV : CACHEINV
bits : 1 - 1 (1 bit)

WAYSEL : WAYSEL
bits : 2 - 2 (1 bit)

HITMEN : HITMEN
bits : 16 - 16 (1 bit)

MISSMEN : MISSMEN
bits : 17 - 17 (1 bit)

HITMRST : HITMRST
bits : 18 - 18 (1 bit)

MISSMRST : MISSMRST
bits : 19 - 19 (1 bit)


ICACHE_HMONR

ICACHE hit monitor register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICACHE_HMONR ICACHE_HMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HITMON

HITMON : HITMON
bits : 0 - 31 (32 bit)


ICACHE_MMONR

ICACHE miss monitor register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICACHE_MMONR ICACHE_MMONR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISSMON

MISSMON : MISSMON
bits : 0 - 15 (16 bit)


ICACHE_CRR0

ICACHE region configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_CRR0 ICACHE_CRR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR RSIZE REN REMAPADDR MSTSEL HBURST

BASEADDR : BASEADDR
bits : 0 - 7 (8 bit)

RSIZE : RSIZE
bits : 9 - 11 (3 bit)

REN : REN
bits : 15 - 15 (1 bit)

REMAPADDR : REMAPADDR
bits : 16 - 26 (11 bit)

MSTSEL : MSTSEL
bits : 28 - 28 (1 bit)

HBURST : HBURST
bits : 31 - 31 (1 bit)


ICACHE_CRR1

ICACHE region configuration register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_CRR1 ICACHE_CRR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR RSIZE REN REMAPADDR MSTSEL HBURST

BASEADDR : BASEADDR
bits : 0 - 7 (8 bit)

RSIZE : RSIZE
bits : 9 - 11 (3 bit)

REN : REN
bits : 15 - 15 (1 bit)

REMAPADDR : REMAPADDR
bits : 16 - 26 (11 bit)

MSTSEL : MSTSEL
bits : 28 - 28 (1 bit)

HBURST : HBURST
bits : 31 - 31 (1 bit)


ICACHE_CRR2

ICACHE region configuration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_CRR2 ICACHE_CRR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR RSIZE REN REMAPADDR MSTSEL HBURST

BASEADDR : BASEADDR
bits : 0 - 7 (8 bit)

RSIZE : RSIZE
bits : 9 - 11 (3 bit)

REN : REN
bits : 15 - 15 (1 bit)

REMAPADDR : REMAPADDR
bits : 16 - 26 (11 bit)

MSTSEL : MSTSEL
bits : 28 - 28 (1 bit)

HBURST : HBURST
bits : 31 - 31 (1 bit)


ICACHE_CRR3

ICACHE region configuration register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_CRR3 ICACHE_CRR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR RSIZE REN REMAPADDR MSTSEL HBURST

BASEADDR : BASEADDR
bits : 0 - 7 (8 bit)

RSIZE : RSIZE
bits : 9 - 11 (3 bit)

REN : REN
bits : 15 - 15 (1 bit)

REMAPADDR : REMAPADDR
bits : 16 - 26 (11 bit)

MSTSEL : MSTSEL
bits : 28 - 28 (1 bit)

HBURST : HBURST
bits : 31 - 31 (1 bit)


ICACHE_SR

ICACHE status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICACHE_SR ICACHE_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYF BSYENDF ERRF

BUSYF : BUSYF
bits : 0 - 0 (1 bit)

BSYENDF : BSYENDF
bits : 1 - 1 (1 bit)

ERRF : ERRF
bits : 2 - 2 (1 bit)


ICACHE_IER

ICACHE interrupt enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICACHE_IER ICACHE_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSYENDIE ERRIE

BSYENDIE : BSYENDIE
bits : 1 - 1 (1 bit)

ERRIE : ERRIE
bits : 2 - 2 (1 bit)


ICACHE_FCR

ICACHE flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICACHE_FCR ICACHE_FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBSYENDF CERRF

CBSYENDF : CBSYENDF
bits : 1 - 1 (1 bit)

CERRF : CERRF
bits : 2 - 2 (1 bit)



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