Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection : not protected
USB PHY Power-Down Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPWDFS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
End of enumeration elements list.
TXPWDIBIAS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
End of enumeration elements list.
TXPWDV2I : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY transmit V-to-I converter and the current mirror
End of enumeration elements list.
RXPWDENV : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed receiver envelope detector (squelch signal)
End of enumeration elements list.
RXPWD1PT1 : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed differential receiver.
End of enumeration elements list.
RXPWDDIFF : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed differential receive
End of enumeration elements list.
RXPWDRX : This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the entire USB PHY receiver block except for the full-speed differential receiver
End of enumeration elements list.
USB PHY Transmitter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_CAL : Decode to trim the nominal 17
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : value0
Maximum current, approximately 19% above nominal.
0x7 : value7
Nominal
0xF : value15
Minimum current, approximately 19% below nominal.
End of enumeration elements list.
TXCAL45DM : Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin
bits : 8 - 11 (4 bit)
access : read-write
TXENCAL45DN : Enable resistance calibration on DN.
bits : 13 - 13 (1 bit)
access : read-write
TXCAL45DP : Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write
TXENCAL45DP : Enable resistance calibration on DP.
bits : 21 - 21 (1 bit)
access : read-write
USB PHY Analog Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVI_EN : Vow voltage detector enable bit.
bits : 1 - 1 (1 bit)
access : read-write
PFD_CLK_SEL : For normal USB operation, this bit field must remain at value 2'b00.
bits : 2 - 3 (2 bit)
access : read-write
DEV_PULLDOWN : Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
0x1 : value1
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
End of enumeration elements list.
USB PHY Analog Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVI_EN : Vow voltage detector enable bit.
bits : 1 - 1 (1 bit)
access : read-write
PFD_CLK_SEL : For normal USB operation, this bit field must remain at value 2'b00.
bits : 2 - 3 (2 bit)
access : read-write
DEV_PULLDOWN : Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
0x1 : value1
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
End of enumeration elements list.
USB PHY Analog Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVI_EN : Vow voltage detector enable bit.
bits : 1 - 1 (1 bit)
access : read-write
PFD_CLK_SEL : For normal USB operation, this bit field must remain at value 2'b00.
bits : 2 - 3 (2 bit)
access : read-write
DEV_PULLDOWN : Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
0x1 : value1
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
End of enumeration elements list.
USB PHY Analog Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVI_EN : Vow voltage detector enable bit.
bits : 1 - 1 (1 bit)
access : read-write
PFD_CLK_SEL : For normal USB operation, this bit field must remain at value 2'b00.
bits : 2 - 3 (2 bit)
access : read-write
DEV_PULLDOWN : Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
0x1 : value1
The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
End of enumeration elements list.
USB PHY Transmitter Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_CAL : Decode to trim the nominal 17
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : value0
Maximum current, approximately 19% above nominal.
0x7 : value7
Nominal
0xF : value15
Minimum current, approximately 19% below nominal.
End of enumeration elements list.
TXCAL45DM : Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin
bits : 8 - 11 (4 bit)
access : read-write
TXENCAL45DN : Enable resistance calibration on DN.
bits : 13 - 13 (1 bit)
access : read-write
TXCAL45DP : Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write
TXENCAL45DP : Enable resistance calibration on DP.
bits : 21 - 21 (1 bit)
access : read-write
USB PHY Transmitter Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_CAL : Decode to trim the nominal 17
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : value0
Maximum current, approximately 19% above nominal.
0x7 : value7
Nominal
0xF : value15
Minimum current, approximately 19% below nominal.
End of enumeration elements list.
TXCAL45DM : Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin
bits : 8 - 11 (4 bit)
access : read-write
TXENCAL45DN : Enable resistance calibration on DN.
bits : 13 - 13 (1 bit)
access : read-write
TXCAL45DP : Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write
TXENCAL45DP : Enable resistance calibration on DP.
bits : 21 - 21 (1 bit)
access : read-write
USB PHY Transmitter Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_CAL : Decode to trim the nominal 17
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : value0
Maximum current, approximately 19% above nominal.
0x7 : value7
Nominal
0xF : value15
Minimum current, approximately 19% below nominal.
End of enumeration elements list.
TXCAL45DM : Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin
bits : 8 - 11 (4 bit)
access : read-write
TXENCAL45DN : Enable resistance calibration on DN.
bits : 13 - 13 (1 bit)
access : read-write
TXCAL45DP : Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin
bits : 16 - 19 (4 bit)
access : read-write
TXENCAL45DP : Enable resistance calibration on DP.
bits : 21 - 21 (1 bit)
access : read-write
USB PHY Receiver Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.1000 V
0x1 : value1
Trip-Level Voltage is 0.1125 V
0x2 : value2
Trip-Level Voltage is 0.1250 V
0x3 : value3
Trip-Level Voltage is 0.0875 V
End of enumeration elements list.
DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.56875 V
0x1 : value1
Trip-Level Voltage is 0.55000 V
0x2 : value2
Trip-Level Voltage is 0.58125 V
0x3 : value3
Trip-Level Voltage is 0.60000 V
End of enumeration elements list.
RXDBYPASS : This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
End of enumeration elements list.
USB PHY Receiver Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.1000 V
0x1 : value1
Trip-Level Voltage is 0.1125 V
0x2 : value2
Trip-Level Voltage is 0.1250 V
0x3 : value3
Trip-Level Voltage is 0.0875 V
End of enumeration elements list.
DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.56875 V
0x1 : value1
Trip-Level Voltage is 0.55000 V
0x2 : value2
Trip-Level Voltage is 0.58125 V
0x3 : value3
Trip-Level Voltage is 0.60000 V
End of enumeration elements list.
RXDBYPASS : This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
End of enumeration elements list.
USB PHY Receiver Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.1000 V
0x1 : value1
Trip-Level Voltage is 0.1125 V
0x2 : value2
Trip-Level Voltage is 0.1250 V
0x3 : value3
Trip-Level Voltage is 0.0875 V
End of enumeration elements list.
DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.56875 V
0x1 : value1
Trip-Level Voltage is 0.55000 V
0x2 : value2
Trip-Level Voltage is 0.58125 V
0x3 : value3
Trip-Level Voltage is 0.60000 V
End of enumeration elements list.
RXDBYPASS : This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
End of enumeration elements list.
USB PHY Receiver Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : The ENVADJ field adjusts the trip point for the envelope detector
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.1000 V
0x1 : value1
Trip-Level Voltage is 0.1125 V
0x2 : value2
Trip-Level Voltage is 0.1250 V
0x3 : value3
Trip-Level Voltage is 0.0875 V
End of enumeration elements list.
DISCONADJ : The DISCONADJ field adjusts the trip point for the disconnect detector.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : value0
Trip-Level Voltage is 0.56875 V
0x1 : value1
Trip-Level Voltage is 0.55000 V
0x2 : value2
Trip-Level Voltage is 0.58125 V
0x3 : value3
Trip-Level Voltage is 0.60000 V
End of enumeration elements list.
RXDBYPASS : This test mode is intended for lab use only, replace FS differential receiver with DP single ended receiver
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
End of enumeration elements list.
USB PHY General Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in High-Speed mode
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDET : Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : value0
Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
0x1 : value1
Enables 200kohm pullup resistors on USB_DP and USB_DM pins
End of enumeration elements list.
DEVPLUGIN_POLARITY : Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write
RESUMEIRQSTICKY : Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : Resume IRQ: Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write
DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write
ENUTMILEVEL2 : Enables UTMI+ Level 2 operation for the USB HS PHY
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : Enables UTMI+ Level 3 operation for the USB HS PHY
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : Enable wake-up IRQ: Enables interrupt for the wake-up events.
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : Wake-up IRQ: Indicates that there is a wak-eup event
bits : 17 - 17 (1 bit)
access : read-write
AUTORESUME_EN : Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : Enable DP DM change wake-up: Not for customer use
bits : 21 - 21 (1 bit)
access : read-write
ENVBUSCHG_WKUP : Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended
bits : 23 - 23 (1 bit)
access : read-write
ENAUTOCLR_USBCLKGATE : Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 25 - 25 (1 bit)
access : read-write
ENAUTOSET_USBCLKS : Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 26 - 26 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with low-speed timing
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in High-Speed mode
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDET : Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : value0
Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
0x1 : value1
Enables 200kohm pullup resistors on USB_DP and USB_DM pins
End of enumeration elements list.
DEVPLUGIN_POLARITY : Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write
RESUMEIRQSTICKY : Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : Resume IRQ: Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write
DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write
ENUTMILEVEL2 : Enables UTMI+ Level 2 operation for the USB HS PHY
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : Enables UTMI+ Level 3 operation for the USB HS PHY
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : Enable wake-up IRQ: Enables interrupt for the wake-up events.
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : Wake-up IRQ: Indicates that there is a wak-eup event
bits : 17 - 17 (1 bit)
access : read-write
AUTORESUME_EN : Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : Enable DP DM change wake-up: Not for customer use
bits : 21 - 21 (1 bit)
access : read-write
ENVBUSCHG_WKUP : Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended
bits : 23 - 23 (1 bit)
access : read-write
ENAUTOCLR_USBCLKGATE : Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 25 - 25 (1 bit)
access : read-write
ENAUTOSET_USBCLKS : Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 26 - 26 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with low-speed timing
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-only
CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in High-Speed mode
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDET : Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : value0
Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
0x1 : value1
Enables 200kohm pullup resistors on USB_DP and USB_DM pins
End of enumeration elements list.
DEVPLUGIN_POLARITY : Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write
RESUMEIRQSTICKY : Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : Resume IRQ: Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write
DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write
ENUTMILEVEL2 : Enables UTMI+ Level 2 operation for the USB HS PHY
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : Enables UTMI+ Level 3 operation for the USB HS PHY
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : Enable wake-up IRQ: Enables interrupt for the wake-up events.
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : Wake-up IRQ: Indicates that there is a wak-eup event
bits : 17 - 17 (1 bit)
access : read-write
AUTORESUME_EN : Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : Enable DP DM change wake-up: Not for customer use
bits : 21 - 21 (1 bit)
access : read-write
ENVBUSCHG_WKUP : Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended
bits : 23 - 23 (1 bit)
access : read-write
ENAUTOCLR_USBCLKGATE : Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 25 - 25 (1 bit)
access : read-write
ENAUTOSET_USBCLKS : Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 26 - 26 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with low-speed timing
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHOSTDISCONDETECT : For host mode, enables high-speed disconnect detector
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : Indicates that the device has disconnected in High-Speed mode
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDET : Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : value0
Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
0x1 : value1
Enables 200kohm pullup resistors on USB_DP and USB_DM pins
End of enumeration elements list.
DEVPLUGIN_POLARITY : Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in
bits : 5 - 5 (1 bit)
access : read-write
RESUMEIRQSTICKY : Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : Resume IRQ: Indicates that the host is sending a wake-up after suspend
bits : 10 - 10 (1 bit)
access : read-write
DEVPLUGIN_IRQ : Indicates that the device is connected
bits : 12 - 12 (1 bit)
access : read-write
ENUTMILEVEL2 : Enables UTMI+ Level 2 operation for the USB HS PHY
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : Enables UTMI+ Level 3 operation for the USB HS PHY
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : Enable wake-up IRQ: Enables interrupt for the wake-up events.
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : Wake-up IRQ: Indicates that there is a wak-eup event
bits : 17 - 17 (1 bit)
access : read-write
AUTORESUME_EN : Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : Enable DP DM change wake-up: Not for customer use
bits : 21 - 21 (1 bit)
access : read-write
ENVBUSCHG_WKUP : Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended
bits : 23 - 23 (1 bit)
access : read-write
ENAUTOCLR_USBCLKGATE : Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 25 - 25 (1 bit)
access : read-write
ENAUTOSET_USBCLKS : Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended
bits : 26 - 26 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : Forces the next FS packet that is transmitted to have a EOP with low-speed timing
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : Used by the PHY to indicate a powered-down state
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : Gate UTMI Clocks
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers
bits : 31 - 31 (1 bit)
access : read-write
USB PHY Power-Down Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPWDFS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
End of enumeration elements list.
TXPWDIBIAS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
End of enumeration elements list.
TXPWDV2I : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY transmit V-to-I converter and the current mirror
End of enumeration elements list.
RXPWDENV : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed receiver envelope detector (squelch signal)
End of enumeration elements list.
RXPWD1PT1 : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed differential receiver.
End of enumeration elements list.
RXPWDDIFF : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed differential receive
End of enumeration elements list.
RXPWDRX : This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the entire USB PHY receiver block except for the full-speed differential receiver
End of enumeration elements list.
USB PHY Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OK_STATUS_3V : Indicates the USB 3v power rails are in range.
bits : 0 - 0 (1 bit)
access : read-only
HOSTDISCONDETECT_STATUS : Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : value0
USB cable disconnect has not been detected at the local host
0x1 : value1
USB cable disconnect has been detected at the local host
End of enumeration elements list.
DEVPLUGIN_STATUS : Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4]
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : value0
No attachment to a USB host is detected
0x1 : value1
Cable attachment to a USB host is detected
End of enumeration elements list.
RESUME_STATUS : Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt.
bits : 10 - 10 (1 bit)
access : read-only
USB PHY Power-Down Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPWDFS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
End of enumeration elements list.
TXPWDIBIAS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
End of enumeration elements list.
TXPWDV2I : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY transmit V-to-I converter and the current mirror
End of enumeration elements list.
RXPWDENV : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed receiver envelope detector (squelch signal)
End of enumeration elements list.
RXPWD1PT1 : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed differential receiver.
End of enumeration elements list.
RXPWDDIFF : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed differential receive
End of enumeration elements list.
RXPWDRX : This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the entire USB PHY receiver block except for the full-speed differential receiver
End of enumeration elements list.
USB PHY PLL Control/Status Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_EN_USB_CLKS : Enables the USB clock from PLL to USB PHY
bits : 6 - 6 (1 bit)
access : read-write
PLL_POWER : Power up the USB PLL
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENABLE : Enables the clock output from the USB PLL
bits : 13 - 13 (1 bit)
access : read-write
REFBIAS_PWD_SEL : Reference bias power down select.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Selects PLL_POWER to control the reference bias
0x1 : value1
Selects REFBIAS_PWD to control the reference bias
End of enumeration elements list.
REFBIAS_PWD : Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
bits : 20 - 20 (1 bit)
access : read-write
PLL_REG_ENABLE : This field controls the USB PLL regulator, set to enable the regulator
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV_SEL : This field controls the USB PLL feedback loop divider
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : value0
Divide by 13
0x1 : value1
Divide by 15
0x2 : value2
Divide by 16
0x3 : value3
Divide by 20
0x4 : value4
Divide by 22
0x5 : value5
Divide by 25
0x6 : value6
Divide by 30
0x7 : value7
Divide by 240
End of enumeration elements list.
PLL_PREDIV : This is selection between /1 or /2 to expand the range of ref input clock.
bits : 30 - 30 (1 bit)
access : read-write
PLL_LOCK : USB PLL lock status indicator
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : value0
PLL is not currently locked
0x1 : value1
PLL is currently locked
End of enumeration elements list.
USB PHY PLL Control/Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_EN_USB_CLKS : Enables the USB clock from PLL to USB PHY
bits : 6 - 6 (1 bit)
access : read-write
PLL_POWER : Power up the USB PLL
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENABLE : Enables the clock output from the USB PLL
bits : 13 - 13 (1 bit)
access : read-write
REFBIAS_PWD_SEL : Reference bias power down select.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Selects PLL_POWER to control the reference bias
0x1 : value1
Selects REFBIAS_PWD to control the reference bias
End of enumeration elements list.
REFBIAS_PWD : Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
bits : 20 - 20 (1 bit)
access : read-write
PLL_REG_ENABLE : This field controls the USB PLL regulator, set to enable the regulator
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV_SEL : This field controls the USB PLL feedback loop divider
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : value0
Divide by 13
0x1 : value1
Divide by 15
0x2 : value2
Divide by 16
0x3 : value3
Divide by 20
0x4 : value4
Divide by 22
0x5 : value5
Divide by 25
0x6 : value6
Divide by 30
0x7 : value7
Divide by 240
End of enumeration elements list.
PLL_PREDIV : This is selection between /1 or /2 to expand the range of ref input clock.
bits : 30 - 30 (1 bit)
access : read-write
PLL_LOCK : USB PLL lock status indicator
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : value0
PLL is not currently locked
0x1 : value1
PLL is currently locked
End of enumeration elements list.
USB PHY PLL Control/Status Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_EN_USB_CLKS : Enables the USB clock from PLL to USB PHY
bits : 6 - 6 (1 bit)
access : read-write
PLL_POWER : Power up the USB PLL
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENABLE : Enables the clock output from the USB PLL
bits : 13 - 13 (1 bit)
access : read-write
REFBIAS_PWD_SEL : Reference bias power down select.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Selects PLL_POWER to control the reference bias
0x1 : value1
Selects REFBIAS_PWD to control the reference bias
End of enumeration elements list.
REFBIAS_PWD : Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
bits : 20 - 20 (1 bit)
access : read-write
PLL_REG_ENABLE : This field controls the USB PLL regulator, set to enable the regulator
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV_SEL : This field controls the USB PLL feedback loop divider
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : value0
Divide by 13
0x1 : value1
Divide by 15
0x2 : value2
Divide by 16
0x3 : value3
Divide by 20
0x4 : value4
Divide by 22
0x5 : value5
Divide by 25
0x6 : value6
Divide by 30
0x7 : value7
Divide by 240
End of enumeration elements list.
PLL_PREDIV : This is selection between /1 or /2 to expand the range of ref input clock.
bits : 30 - 30 (1 bit)
access : read-write
PLL_LOCK : USB PLL lock status indicator
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : value0
PLL is not currently locked
0x1 : value1
PLL is currently locked
End of enumeration elements list.
USB PHY PLL Control/Status Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_EN_USB_CLKS : Enables the USB clock from PLL to USB PHY
bits : 6 - 6 (1 bit)
access : read-write
PLL_POWER : Power up the USB PLL
bits : 12 - 12 (1 bit)
access : read-write
PLL_ENABLE : Enables the clock output from the USB PLL
bits : 13 - 13 (1 bit)
access : read-write
REFBIAS_PWD_SEL : Reference bias power down select.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Selects PLL_POWER to control the reference bias
0x1 : value1
Selects REFBIAS_PWD to control the reference bias
End of enumeration elements list.
REFBIAS_PWD : Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
bits : 20 - 20 (1 bit)
access : read-write
PLL_REG_ENABLE : This field controls the USB PLL regulator, set to enable the regulator
bits : 21 - 21 (1 bit)
access : read-write
PLL_DIV_SEL : This field controls the USB PLL feedback loop divider
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
0 : value0
Divide by 13
0x1 : value1
Divide by 15
0x2 : value2
Divide by 16
0x3 : value3
Divide by 20
0x4 : value4
Divide by 22
0x5 : value5
Divide by 25
0x6 : value6
Divide by 30
0x7 : value7
Divide by 240
End of enumeration elements list.
PLL_PREDIV : This is selection between /1 or /2 to expand the range of ref input clock.
bits : 30 - 30 (1 bit)
access : read-write
PLL_LOCK : USB PLL lock status indicator
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : value0
PLL is not currently locked
0x1 : value1
PLL is currently locked
End of enumeration elements list.
USB PHY Power-Down Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPWDFS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
End of enumeration elements list.
TXPWDIBIAS : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
End of enumeration elements list.
TXPWDV2I : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB PHY transmit V-to-I converter and the current mirror
End of enumeration elements list.
RXPWDENV : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed receiver envelope detector (squelch signal)
End of enumeration elements list.
RXPWD1PT1 : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB full-speed differential receiver.
End of enumeration elements list.
RXPWDDIFF : Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the USB high-speed differential receive
End of enumeration elements list.
RXPWDRX : This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : value0
Normal operation.
0x1 : value1
Power-down the entire USB PHY receiver block except for the full-speed differential receiver
End of enumeration elements list.
USB PHY VBUS Detect Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSVALID_THRESH : Sets the threshold for the VBUSVALID comparator
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
4.0V
0x1 : value1
4.1V
0x2 : value2
4.2V
0x3 : value3
4.3V
0x4 : value4
4.4V(Default)
0x5 : value5
4.5V
0x6 : value6
4.6V
0x7 : value7
4.7V
End of enumeration elements list.
VBUS_OVERRIDE_EN : VBUS detect signal override enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
0x1 : value1
Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
End of enumeration elements list.
SESSEND_OVERRIDE : Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 4 - 4 (1 bit)
access : read-write
BVALID_OVERRIDE : Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 5 - 5 (1 bit)
access : read-write
AVALID_OVERRIDE : Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 6 - 6 (1 bit)
access : read-write
VBUSVALID_OVERRIDE : Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1
bits : 7 - 7 (1 bit)
access : read-write
VBUSVALID_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the VBUS_VALID_3V detector results for signal reported to the USB controller
End of enumeration elements list.
VBUS_SOURCE_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the Session Valid comparator results for signal reported to the USB controller
0x2 : value2
Use the Session Valid comparator results for signal reported to the USB controller
End of enumeration elements list.
ID_OVERRIDE_EN : Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.
bits : 11 - 11 (1 bit)
access : read-write
ID_OVERRIDE : ID override value.
bits : 12 - 12 (1 bit)
access : read-write
EXT_ID_OVERRIDE_EN : Enable ID override using the pinmuxed value:
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using ID_OVERRIDE_EN.
0x1 : value1
Select the external ID value.
End of enumeration elements list.
EXT_VBUS_OVERRIDE_EN : Enable VBUS override using the pinmuxed value.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using VBUS_OVERRIDE_EN.
0x1 : value1
Select the external VBUS VALID value.
End of enumeration elements list.
VBUSVALID_TO_SESSVALID : Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator for VBUS_VALID results
0x1 : value1
Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
End of enumeration elements list.
VBUSVALID_5VDETECT : no description available
bits : 19 - 19 (1 bit)
access : read-write
PWRUP_CMPS : Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : value0
Powers down the VBUS_VALID comparator
0x7 : value1
Enables the VBUS_VALID comparator (default)
End of enumeration elements list.
DISCHARGE_VBUS : Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : value0
VBUS discharge resistor is disabled (Default)
0x1 : value1
VBUS discharge resistor is enabled
End of enumeration elements list.
USB PHY VBUS Detect Control Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSVALID_THRESH : Sets the threshold for the VBUSVALID comparator
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
4.0V
0x1 : value1
4.1V
0x2 : value2
4.2V
0x3 : value3
4.3V
0x4 : value4
4.4V(Default)
0x5 : value5
4.5V
0x6 : value6
4.6V
0x7 : value7
4.7V
End of enumeration elements list.
VBUS_OVERRIDE_EN : VBUS detect signal override enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
0x1 : value1
Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
End of enumeration elements list.
SESSEND_OVERRIDE : Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 4 - 4 (1 bit)
access : read-write
BVALID_OVERRIDE : Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 5 - 5 (1 bit)
access : read-write
AVALID_OVERRIDE : Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 6 - 6 (1 bit)
access : read-write
VBUSVALID_OVERRIDE : Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1
bits : 7 - 7 (1 bit)
access : read-write
VBUSVALID_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the VBUS_VALID_3V detector results for signal reported to the USB controller
End of enumeration elements list.
VBUS_SOURCE_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the Session Valid comparator results for signal reported to the USB controller
0x2 : value2
Use the Session Valid comparator results for signal reported to the USB controller
End of enumeration elements list.
ID_OVERRIDE_EN : Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.
bits : 11 - 11 (1 bit)
access : read-write
ID_OVERRIDE : ID override value.
bits : 12 - 12 (1 bit)
access : read-write
EXT_ID_OVERRIDE_EN : Enable ID override using the pinmuxed value:
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using ID_OVERRIDE_EN.
0x1 : value1
Select the external ID value.
End of enumeration elements list.
EXT_VBUS_OVERRIDE_EN : Enable VBUS override using the pinmuxed value.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using VBUS_OVERRIDE_EN.
0x1 : value1
Select the external VBUS VALID value.
End of enumeration elements list.
VBUSVALID_TO_SESSVALID : Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator for VBUS_VALID results
0x1 : value1
Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
End of enumeration elements list.
VBUSVALID_5VDETECT : no description available
bits : 19 - 19 (1 bit)
access : read-write
PWRUP_CMPS : Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : value0
Powers down the VBUS_VALID comparator
0x7 : value1
Enables the VBUS_VALID comparator (default)
End of enumeration elements list.
DISCHARGE_VBUS : Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : value0
VBUS discharge resistor is disabled (Default)
0x1 : value1
VBUS discharge resistor is enabled
End of enumeration elements list.
USB PHY VBUS Detect Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSVALID_THRESH : Sets the threshold for the VBUSVALID comparator
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
4.0V
0x1 : value1
4.1V
0x2 : value2
4.2V
0x3 : value3
4.3V
0x4 : value4
4.4V(Default)
0x5 : value5
4.5V
0x6 : value6
4.6V
0x7 : value7
4.7V
End of enumeration elements list.
VBUS_OVERRIDE_EN : VBUS detect signal override enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
0x1 : value1
Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
End of enumeration elements list.
SESSEND_OVERRIDE : Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 4 - 4 (1 bit)
access : read-write
BVALID_OVERRIDE : Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 5 - 5 (1 bit)
access : read-write
AVALID_OVERRIDE : Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 6 - 6 (1 bit)
access : read-write
VBUSVALID_OVERRIDE : Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1
bits : 7 - 7 (1 bit)
access : read-write
VBUSVALID_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the VBUS_VALID_3V detector results for signal reported to the USB controller
End of enumeration elements list.
VBUS_SOURCE_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the Session Valid comparator results for signal reported to the USB controller
0x2 : value2
Use the Session Valid comparator results for signal reported to the USB controller
End of enumeration elements list.
ID_OVERRIDE_EN : Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.
bits : 11 - 11 (1 bit)
access : read-write
ID_OVERRIDE : ID override value.
bits : 12 - 12 (1 bit)
access : read-write
EXT_ID_OVERRIDE_EN : Enable ID override using the pinmuxed value:
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using ID_OVERRIDE_EN.
0x1 : value1
Select the external ID value.
End of enumeration elements list.
EXT_VBUS_OVERRIDE_EN : Enable VBUS override using the pin muxed value.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the muxed value chosen using VBUS_OVERRIDE_EN.
0x1 : value1
Select the external VBUS VALID value.
End of enumeration elements list.
VBUSVALID_TO_SESSVALID : Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator for VBUS_VALID results
0x1 : value1
Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
End of enumeration elements list.
VBUSVALID_5VDETECT : no description available
bits : 19 - 19 (1 bit)
access : read-write
PWRUP_CMPS : Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : value0
Powers down the VBUS_VALID comparator
0x7 : value1
Enables the VBUS_VALID comparator (default)
End of enumeration elements list.
DISCHARGE_VBUS : Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : value0
VBUS discharge resistor is disabled (Default)
0x1 : value1
VBUS discharge resistor is enabled
End of enumeration elements list.
USB PHY VBUS Detect Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSVALID_THRESH : Sets the threshold for the VBUSVALID comparator
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : value0
4.0V
0x1 : value1
4.1V
0x2 : value2
4.2V
0x3 : value3
4.3V
0x4 : value4
4.4V(Default)
0x5 : value5
4.5V
0x6 : value6
4.6V
0x7 : value7
4.7V
End of enumeration elements list.
VBUS_OVERRIDE_EN : VBUS detect signal override enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
0x1 : value1
Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
End of enumeration elements list.
SESSEND_OVERRIDE : Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 4 - 4 (1 bit)
access : read-write
BVALID_OVERRIDE : Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 5 - 5 (1 bit)
access : read-write
AVALID_OVERRIDE : Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1
bits : 6 - 6 (1 bit)
access : read-write
VBUSVALID_OVERRIDE : Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1
bits : 7 - 7 (1 bit)
access : read-write
VBUSVALID_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the VBUS_VALID_3V detector results for signal reported to the USB controller
End of enumeration elements list.
VBUS_SOURCE_SEL : Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
0x1 : value1
Use the Session Valid comparator results for signal reported to the USB controller
0x2 : value2
Use the Session Valid comparator results for signal reported to the USB controller
End of enumeration elements list.
ID_OVERRIDE_EN : Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0.
bits : 11 - 11 (1 bit)
access : read-write
ID_OVERRIDE : ID override value.
bits : 12 - 12 (1 bit)
access : read-write
EXT_ID_OVERRIDE_EN : Enable ID override using the pin muxed value.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the muxed value chosen using ID_OVERRIDE_EN.
0x1 : value1
Select the external ID value.
End of enumeration elements list.
EXT_VBUS_OVERRIDE_EN : Enable VBUS override using the pin muxed value.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : value0
Select the Muxed value chosen using VBUS_OVERRIDE_EN.
0x1 : value1
Select the external VBUS VALID value.
End of enumeration elements list.
VBUSVALID_TO_SESSVALID : Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : value0
Use the VBUS_VALID comparator for VBUS_VALID results
0x1 : value1
Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
End of enumeration elements list.
VBUSVALID_5VDETECT : no description available
bits : 19 - 19 (1 bit)
access : read-write
PWRUP_CMPS : Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : value0
Powers down the VBUS_VALID comparator
0x7 : value1
Enables the VBUS_VALID comparator (default)
End of enumeration elements list.
DISCHARGE_VBUS : Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : value0
VBUS discharge resistor is disabled (Default)
0x1 : value1
VBUS discharge resistor is enabled
End of enumeration elements list.
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