Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RES : Resolution
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : RES_0
Up to 13-bit differential/12-bit single ended resolution supported.
0x1 : RES_1
Up to 16-bit differential/16-bit single ended resolution supported.
End of enumeration elements list.
DIFFEN : Differential Supported
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : DIFFEN_0
Differential operation not supported.
0x1 : DIFFEN_1
Differential operation supported. CMDLa[CTYPE] controls fields implemented.
End of enumeration elements list.
MVI : Multi Vref Implemented
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : MVI_0
Single voltage reference high (VREFH) input supported.
0x1 : MVI_1
Multiple voltage reference high (VREFH) inputs supported.
End of enumeration elements list.
CSW : Channel Scale Width
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
0 : CSW_0
Channel scaling not supported.
0x1 : CSW_1
Channel scaling supported. 1-bit CSCALE control field.
0x6 : CSW_6
Channel scaling supported. 6-bit CSCALE control field.
End of enumeration elements list.
VR1RNGI : Voltage Reference 1 Range Control Bit Implemented
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : VR1RNGI_0
Range control not required. CFG[VREF1RNG] is not implemented.
0x1 : VR1RNGI_1
Range control required. CFG[VREF1RNG] is implemented.
End of enumeration elements list.
IADCKI : Internal ADC Clock implemented
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : IADCKI_0
Internal clock source not implemented.
0x1 : IADCKI_1
Internal clock source (and CFG[ADCKEN]) implemented.
End of enumeration elements list.
CALOFSI : Calibration Function Implemented
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : CALOFSI_0
Calibration Not Implemented.
0x1 : CALOFSI_1
Calibration Implemented.
End of enumeration elements list.
NUM_SEC : Number of Single Ended Outputs Supported
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : NUM_SEC_0
This design supports one single ended conversion at a time.
0x1 : NUM_SEC_1
This design supports two simultanious single ended conversions.
End of enumeration elements list.
NUM_FIFO : Number of FIFOs
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
0 : NUM_FIFO_0
N/A
0x1 : NUM_FIFO_1
This design supports one result FIFO.
0x2 : NUM_FIFO_2
This design supports two result FIFOs.
0x3 : NUM_FIFO_3
This design supports three result FIFOs.
0x4 : NUM_FIFO_4
This design supports four result FIFOs.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
ADC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : ADC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ADCEN_0
ADC is disabled.
0x1 : ADCEN_1
ADC is enabled.
End of enumeration elements list.
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : RST_0
ADC logic is not reset.
0x1 : RST_1
ADC logic is reset.
End of enumeration elements list.
DOZEN : Doze Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DOZEN_0
ADC is enabled in Doze mode.
0x1 : DOZEN_1
ADC is disabled in Doze mode.
End of enumeration elements list.
CAL_REQ : Auto-Calibration Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CAL_REQ_0
No request for auto-calibration has been made.
0x1 : CAL_REQ_1
A request for auto-calibration has been made
End of enumeration elements list.
CALOFS : Configure for offset calibration function
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CALOFS_0
Calibration function disabled
0x1 : CALOFS_1
Request for offset calibration function
End of enumeration elements list.
RSTFIFO0 : Reset FIFO 0
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : RSTFIFO0_0
No effect.
0x1 : RSTFIFO0_1
FIFO 0 is reset.
End of enumeration elements list.
RSTFIFO1 : Reset FIFO 1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : RSTFIFO1_0
No effect.
0x1 : RSTFIFO1_1
FIFO 1 is reset.
End of enumeration elements list.
CAL_AVGS : Auto-Calibration Averages
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : CAL_AVGS_0
Single conversion.
0x1 : CAL_AVGS_1
2 conversions averaged.
0x2 : CAL_AVGS_2
4 conversions averaged.
0x3 : CAL_AVGS_3
8 conversions averaged.
0x4 : CAL_AVGS_4
16 conversions averaged.
0x5 : CAL_AVGS_5
32 conversions averaged.
0x6 : CAL_AVGS_6
64 conversions averaged.
0x7 : CAL_AVGS_7
128 conversions averaged.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Command High Buffer Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Function Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CMPEN_0
Compare disabled.
0x2 : CMPEN_2
Compare enabled. Store on true.
0x3 : CMPEN_3
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
End of enumeration elements list.
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Function Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CMPEN_0
Compare disabled.
0x2 : CMPEN_2
Compare enabled. Store on true.
0x3 : CMPEN_3
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
End of enumeration elements list.
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Function Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CMPEN_0
Compare disabled.
0x2 : CMPEN_2
Compare enabled. Store on true.
0x3 : CMPEN_3
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
End of enumeration elements list.
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Function Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : CMPEN_0
Compare disabled.
0x2 : CMPEN_2
Compare enabled. Store on true.
0x3 : CMPEN_3
Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
End of enumeration elements list.
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDY0 : Result FIFO 0 Ready Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : RDY0_0
Result FIFO 0 data level not above watermark level.
0x1 : RDY0_1
Result FIFO 0 holding data above watermark level.
End of enumeration elements list.
FOF0 : Result FIFO 0 Overflow Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FOF0_0
No result FIFO 0 overflow has occurred since the last time the flag was cleared.
0x1 : FOF0_1
At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
RDY1 : Result FIFO1 Ready Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : RDY1_0
Result FIFO1 data level not above watermark level.
0x1 : RDY1_1
Result FIFO1 holding data above watermark level.
End of enumeration elements list.
FOF1 : Result FIFO1 Overflow Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FOF1_0
No result FIFO1 overflow has occurred since the last time the flag was cleared.
0x1 : FOF1_1
At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
TEXC_INT : Interrupt Flag For High Priority Trigger Exception
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TEXC_INT_0
No trigger exceptions have occurred.
0x1 : TEXC_INT_1
A trigger exception has occurred and is pending acknowledgement.
End of enumeration elements list.
TCOMP_INT : Interrupt Flag For Trigger Completion
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TCOMP_INT_0
Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
0x1 : TCOMP_INT_1
Trigger sequence has been completed and all data is stored in the associated FIFO.
End of enumeration elements list.
CAL_RDY : Calibration Ready
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : CAL_RDY_0
Calibration is incomplete or hasn't been ran.
0x1 : CAL_RDY_1
The ADC is calibrated.
End of enumeration elements list.
ADC_ACTIVE : ADC Active
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : ADC_ACTIVE_0
The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
0x1 : ADC_ACTIVE_1
The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
End of enumeration elements list.
TRGACT : Trigger Active
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : TRGACT_0
Command (sequence) associated with Trigger 0 currently being executed.
0x1 : TRGACT_1
Command (sequence) associated with Trigger 1 currently being executed.
0x2 : TRGACT_2
Command (sequence) associated with Trigger 2 currently being executed.
0x3 : TRGACT_3
Command (sequence) from the associated Trigger number is currently being executed.
0x4 : TRGACT_4
Command (sequence) from the associated Trigger number is currently being executed.
0x5 : TRGACT_5
Command (sequence) from the associated Trigger number is currently being executed.
0x6 : TRGACT_6
Command (sequence) from the associated Trigger number is currently being executed.
0x7 : TRGACT_7
Command (sequence) from the associated Trigger number is currently being executed.
0x8 : TRGACT_8
Command (sequence) from the associated Trigger number is currently being executed.
0x9 : TRGACT_9
Command (sequence) from the associated Trigger number is currently being executed.
End of enumeration elements list.
CMDACT : Command Active
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : CMDACT_0
No command is currently in progress.
0x1 : CMDACT_1
Command 1 currently being executed.
0x2 : CMDACT_2
Command 2 currently being executed.
0x3 : CMDACT_3
Associated command number is currently being executed.
0x4 : CMDACT_4
Associated command number is currently being executed.
0x5 : CMDACT_5
Associated command number is currently being executed.
0x6 : CMDACT_6
Associated command number is currently being executed.
0x7 : CMDACT_7
Associated command number is currently being executed.
0x8 : CMDACT_8
Associated command number is currently being executed.
0x9 : CMDACT_9
Associated command number is currently being executed.
End of enumeration elements list.
Trigger Control Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Command High Buffer Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
ADC Command Low Buffer Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ADCH_0
Select CH0A or CH0B or CH0A/CH0B pair.
0x1 : ADCH_1
Select CH1A or CH1B or CH1A/CH1B pair.
0x2 : ADCH_2
Select CH2A or CH2B or CH2A/CH2B pair.
0x3 : ADCH_3
Select CH3A or CH3B or CH3A/CH3B pair.
0x4 : ADCH_4
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x5 : ADCH_5
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x6 : ADCH_6
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x7 : ADCH_7
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x8 : ADCH_8
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x9 : ADCH_9
Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
0x1E : ADCH_30
Select CH30A or CH30B or CH30A/CH30B pair.
0x1F : ADCH_31
Select CH31A or CH31B or CH31A/CH31B pair.
End of enumeration elements list.
CTYPE : Conversion Type
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : CTYPE_0
Single-Ended Mode. Only A side channel is converted.
0x1 : CTYPE_1
Single-Ended Mode. Only B side channel is converted.
0x2 : CTYPE_2
Differential Mode. A-B.
0x3 : CTYPE_3
Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
End of enumeration elements list.
MODE : Select resolution of conversions
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : MODE_0
Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
0x1 : MODE_1
High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
End of enumeration elements list.
ADC Command High Buffer Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAIT_TRIG : Wait for trigger assertion before execution.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : WAIT_TRIG_0
This command will be automatically executed.
0x1 : WAIT_TRIG_1
The active trigger must be asserted again before executing this command.
End of enumeration elements list.
LWI : Loop with Increment
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : LWI_0
Auto channel increment disabled
0x1 : LWI_1
Auto channel increment enabled
End of enumeration elements list.
STS : Sample Time Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : STS_0
Minimum sample time of 3 ADCK cycles.
0x1 : STS_1
3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
0x2 : STS_2
3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
0x3 : STS_3
3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
0x4 : STS_4
3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
0x5 : STS_5
3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
0x6 : STS_6
3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
0x7 : STS_7
3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
End of enumeration elements list.
AVGS : Hardware Average Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : AVGS_0
Single conversion.
0x1 : AVGS_1
2 conversions averaged.
0x2 : AVGS_2
4 conversions averaged.
0x3 : AVGS_3
8 conversions averaged.
0x4 : AVGS_4
16 conversions averaged.
0x5 : AVGS_5
32 conversions averaged.
0x6 : AVGS_6
64 conversions averaged.
0x7 : AVGS_7
128 conversions averaged.
End of enumeration elements list.
LOOP : Loop Count Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : LOOP_0
Looping not enabled. Command executes 1 time.
0x1 : LOOP_1
Loop 1 time. Command executes 2 times.
0x2 : LOOP_2
Loop 2 times. Command executes 3 times.
0x3 : LOOP_3
Loop corresponding number of times. Command executes LOOP+1 times.
0x4 : LOOP_4
Loop corresponding number of times. Command executes LOOP+1 times.
0x5 : LOOP_5
Loop corresponding number of times. Command executes LOOP+1 times.
0x6 : LOOP_6
Loop corresponding number of times. Command executes LOOP+1 times.
0x7 : LOOP_7
Loop corresponding number of times. Command executes LOOP+1 times.
0x8 : LOOP_8
Loop corresponding number of times. Command executes LOOP+1 times.
0x9 : LOOP_9
Loop corresponding number of times. Command executes LOOP+1 times.
0xF : LOOP_15
Loop 15 times. Command executes 16 times.
End of enumeration elements list.
NEXT : Next Command Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : NEXT_0
No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.
0x1 : NEXT_1
Select CMD1 command buffer register as next command.
0x2 : NEXT_2
Select corresponding CMD command buffer register as next command
0x3 : NEXT_3
Select corresponding CMD command buffer register as next command
0x4 : NEXT_4
Select corresponding CMD command buffer register as next command
0x5 : NEXT_5
Select corresponding CMD command buffer register as next command
0x6 : NEXT_6
Select corresponding CMD command buffer register as next command
0x7 : NEXT_7
Select corresponding CMD command buffer register as next command
0x8 : NEXT_8
Select corresponding CMD command buffer register as next command
0x9 : NEXT_9
Select corresponding CMD command buffer register as next command
0xF : NEXT_15
Select CMD15 command buffer register as next command.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWMIE0 : FIFO 0 Watermark Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FWMIE0_0
FIFO 0 watermark interrupts are not enabled.
0x1 : FWMIE0_1
FIFO 0 watermark interrupts are enabled.
End of enumeration elements list.
FOFIE0 : Result FIFO 0 Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FOFIE0_0
FIFO 0 overflow interrupts are not enabled.
0x1 : FOFIE0_1
FIFO 0 overflow interrupts are enabled.
End of enumeration elements list.
FWMIE1 : FIFO1 Watermark Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FWMIE1_0
FIFO1 watermark interrupts are not enabled.
0x1 : FWMIE1_1
FIFO1 watermark interrupts are enabled.
End of enumeration elements list.
FOFIE1 : Result FIFO1 Overflow Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : FOFIE1_0
No result FIFO1 overflow has occurred since the last time the flag was cleared.
0x1 : FOFIE1_1
At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
TEXC_IE : Trigger Exception Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TEXC_IE_0
Trigger exception interrupts are disabled.
0x1 : TEXC_IE_1
Trigger exception interrupts are enabled.
End of enumeration elements list.
TCOMP_IE : Trigger Completion Interrupt Enable
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : TCOMP_IE_0
Trigger completion interrupts are disabled.
0x1 : TCOMP_IE_1
Trigger completion interrupts are enabled for trigger source 0 only.
0x2 : TCOMP_IE_2
Trigger completion interrupts are enabled for trigger source 1 only.
0x3 : TCOMP_IE_3
Associated trigger completion interrupts are enabled.
0x4 : TCOMP_IE_4
Associated trigger completion interrupts are enabled.
0x5 : TCOMP_IE_5
Associated trigger completion interrupts are enabled.
0x6 : TCOMP_IE_6
Associated trigger completion interrupts are enabled.
0x7 : TCOMP_IE_7
Associated trigger completion interrupts are enabled.
0x8 : TCOMP_IE_8
Associated trigger completion interrupts are enabled.
0x9 : TCOMP_IE_9
Associated trigger completion interrupts are enabled.
0xFFFF : TCOMP_IE_65535
Trigger completion interrupts are enabled for every trigger source.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
DMA Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWMDE0 : FIFO 0 Watermark DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FWMDE0_0
DMA request disabled.
0x1 : FWMDE0_1
DMA request enabled.
End of enumeration elements list.
FWMDE1 : FIFO1 Watermark DMA Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FWMDE1_0
DMA request disabled.
0x1 : FWMDE1_1
DMA request enabled.
End of enumeration elements list.
FIFO Control Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCOUNT : Result FIFO counter
bits : 0 - 4 (5 bit)
access : read-only
FWMARK : Watermark level selection
bits : 16 - 19 (4 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x1C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Gain Calibration Control
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GAIN_CAL : Gain Calibration Value
bits : 0 - 15 (16 bit)
access : read-only
RDY : Gain Calibration Value Valid
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : RDY_0
The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
0x1 : RDY_1
The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x1E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Gain Calculation Result
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCALR : Gain Calculation Result
bits : 0 - 15 (16 bit)
access : read-write
RDY : Gain Calculation Ready
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RDY_0
The gain offset calculation value is invalid.
0x1 : RDY_1
The gain calibration value is valid.
End of enumeration elements list.
ADC Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPRICTRL : ADC trigger priority control
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TPRICTRL_0
If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.
0x1 : TPRICTRL_1
If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
0x2 : TPRICTRL_2
If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger.
End of enumeration elements list.
PWRSEL : Power Configuration Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : PWRSEL_0
Lowest power setting.
0x1 : PWRSEL_1
Higher power setting than 0b0.
0x2 : PWRSEL_2
Higher power setting than 0b1.
0x3 : PWRSEL_3
Highest power setting.
End of enumeration elements list.
REFSEL : Voltage Reference Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : REFSEL_0
(Default) Option 1 setting.
0x1 : REFSEL_1
Option 2 setting.
0x2 : REFSEL_2
Option 3 setting.
End of enumeration elements list.
TRES : Trigger Resume Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TRES_0
Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
0x1 : TRES_1
Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
End of enumeration elements list.
TCMDRES : Trigger Command Resume
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TCMDRES_0
Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
0x1 : TCMDRES_1
Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
End of enumeration elements list.
HPT_EXDI : High Priority Trigger Exception Disable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : HPT_EXDI_0
High priority trigger exceptions are enabled.
0x1 : HPT_EXDI_1
High priority trigger exceptions are disabled.
End of enumeration elements list.
PUDLY : Power Up Delay
bits : 16 - 23 (8 bit)
access : read-write
PWREN : ADC Analog Pre-Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : PWREN_0
ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
0x1 : PWREN_1
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x2054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x233C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Pause Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAUSEDLY : Pause Delay
bits : 0 - 8 (9 bit)
access : read-write
PAUSEEN : PAUSE Option Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : PAUSEEN_0
Pause operation disabled
0x1 : PAUSEEN_1
Pause operation enabled
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x2854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x2890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
FIFO Control Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCOUNT : Result FIFO counter
bits : 0 - 4 (5 bit)
access : read-only
FWMARK : Watermark level selection
bits : 16 - 19 (4 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x2CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Gain Calibration Control
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GAIN_CAL : Gain Calibration Value
bits : 0 - 15 (16 bit)
access : read-only
RDY : Gain Calibration Value Valid
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : RDY_0
The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
0x1 : RDY_1
The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x2D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Gain Calculation Result
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCALR : Gain Calculation Result
bits : 0 - 15 (16 bit)
access : read-write
RDY : Gain Calculation Ready
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : RDY_0
The gain offset calculation value is invalid.
0x1 : RDY_1
The gain calibration value is valid.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x3290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Software Trigger Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWT0 : Software trigger 0 event
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SWT0_0
No trigger 0 event generated.
0x1 : SWT0_1
Trigger 0 event generated.
End of enumeration elements list.
SWT1 : Software trigger 1 event
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SWT1_0
No trigger 1 event generated.
0x1 : SWT1_1
Trigger 1 event generated.
End of enumeration elements list.
SWT2 : Software trigger 2 event
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SWT2_0
No trigger 2 event generated.
0x1 : SWT2_1
Trigger 2 event generated.
End of enumeration elements list.
SWT3 : Software trigger 3 event
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SWT3_0
No trigger 3 event generated.
0x1 : SWT3_1
Trigger 3 event generated.
End of enumeration elements list.
SWT4 : Software trigger 4 event
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SWT4_0
No trigger 4 event generated.
0x1 : SWT4_1
Trigger 4 event generated.
End of enumeration elements list.
SWT5 : Software trigger 5 event
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SWT5_0
No trigger 5 event generated.
0x1 : SWT5_1
Trigger 5 event generated.
End of enumeration elements list.
SWT6 : Software trigger 6 event
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SWT6_0
No trigger 6 event generated.
0x1 : SWT6_1
Trigger 6 event generated.
End of enumeration elements list.
SWT7 : Software trigger 7 event
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SWT7_0
No trigger 7 event generated.
0x1 : SWT7_1
Trigger 7 event generated.
End of enumeration elements list.
SWT8 : Software trigger 8 event
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SWT8_0
No trigger 8 event generated.
0x1 : SWT8_1
Trigger 8 event generated.
End of enumeration elements list.
SWT9 : Software trigger 9 event
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SWT9_0
No trigger 9 event generated.
0x1 : SWT9_1
Trigger 9 event generated.
End of enumeration elements list.
SWT10 : Software trigger 10 event
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SWT10_0
No trigger 10 event generated.
0x1 : SWT10_1
Trigger 10 event generated.
End of enumeration elements list.
SWT11 : Software trigger 11 event
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SWT11_0
No trigger 11 event generated.
0x1 : SWT11_1
Trigger 11 event generated.
End of enumeration elements list.
SWT12 : Software trigger 12 event
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SWT12_0
No trigger 12 event generated.
0x1 : SWT12_1
Trigger 12 event generated.
End of enumeration elements list.
SWT13 : Software trigger 13 event
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SWT13_0
No trigger 13 event generated.
0x1 : SWT13_1
Trigger 13 event generated.
End of enumeration elements list.
SWT14 : Software trigger 14 event
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SWT14_0
No trigger 14 event generated.
0x1 : SWT14_1
Trigger 14 event generated.
End of enumeration elements list.
SWT15 : Software trigger 15 event
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SWT15_0
No trigger 15 event generated.
0x1 : SWT15_1
Trigger 15 event generated.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x3508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x37B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEXC_NUM : Trigger Exception Number
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : TEXC_NUM_0
No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
0x1 : TEXC_NUM_1
Trigger 0 has been interrupted by a high priority exception.
0x2 : TEXC_NUM_2
Trigger 1 has been interrupted by a high priority exception.
0x3 : TEXC_NUM_3
Associated trigger sequence has interrupted by a high priority exception.
0x4 : TEXC_NUM_4
Associated trigger sequence has interrupted by a high priority exception.
0x5 : TEXC_NUM_5
Associated trigger sequence has interrupted by a high priority exception.
0x6 : TEXC_NUM_6
Associated trigger sequence has interrupted by a high priority exception.
0x7 : TEXC_NUM_7
Associated trigger sequence has interrupted by a high priority exception.
0x8 : TEXC_NUM_8
Associated trigger sequence has interrupted by a high priority exception.
0x9 : TEXC_NUM_9
Associated trigger sequence has interrupted by a high priority exception.
0xFFFF : TEXC_NUM_65535
Every trigger sequence has been interrupted by a high priority exception.
End of enumeration elements list.
TCOMP_FLAG : Trigger Completion Flag
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : TCOMP_FLAG_0
No triggers have been completed. Trigger completion interrupts are disabled.
0x1 : TCOMP_FLAG_1
Trigger 0 has been completed and triger 0 has enabled completion interrupts.
0x2 : TCOMP_FLAG_2
Trigger 1 has been completed and triger 1 has enabled completion interrupts.
0x3 : TCOMP_FLAG_3
Associated trigger sequence has completed and has enabled completion interrupts.
0x4 : TCOMP_FLAG_4
Associated trigger sequence has completed and has enabled completion interrupts.
0x5 : TCOMP_FLAG_5
Associated trigger sequence has completed and has enabled completion interrupts.
0x6 : TCOMP_FLAG_6
Associated trigger sequence has completed and has enabled completion interrupts.
0x7 : TCOMP_FLAG_7
Associated trigger sequence has completed and has enabled completion interrupts.
0x8 : TCOMP_FLAG_8
Associated trigger sequence has completed and has enabled completion interrupts.
0x9 : TCOMP_FLAG_9
Associated trigger sequence has completed and has enabled completion interrupts.
0xFFFF : TCOMP_FLAG_65535
Every trigger sequence has been completed and every trigger has enabled completion interrupts.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x3938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x3CDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x3D6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRIG_NUM : Trigger Number
bits : 0 - 7 (8 bit)
access : read-only
FIFOSIZE : Result FIFO Depth
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0x1 : FIFOSIZE_1
Result FIFO depth = 1 dataword.
0x4 : FIFOSIZE_4
Result FIFO depth = 4 datawords.
0x8 : FIFOSIZE_8
Result FIFO depth = 8 datawords.
0x10 : FIFOSIZE_16
Result FIFO depth = 16 datawords.
0x20 : FIFOSIZE_32
Result FIFO depth = 32 datawords.
0x40 : FIFOSIZE_64
Result FIFO depth = 64 datawords.
End of enumeration elements list.
CV_NUM : Compare Value Number
bits : 16 - 23 (8 bit)
access : read-only
CMD_NUM : Command Buffer Number
bits : 24 - 31 (8 bit)
access : read-only
ADC Offset Trim Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFSTRIM_A : Trim for offset
bits : 0 - 4 (5 bit)
access : read-write
OFSTRIM_B : Trim for offset
bits : 16 - 20 (5 bit)
access : read-write
Compare Value Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CVL : Compare Value Low.
bits : 0 - 15 (16 bit)
access : read-write
CVH : Compare Value High.
bits : 16 - 31 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x41A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x4208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x45E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x4738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x4A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x4C6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x4E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x51A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x52AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x56E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x56F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x5B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x5C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x5F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Data Result FIFO Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
D : Data result
bits : 0 - 15 (16 bit)
access : read-only
TSRC : Trigger Source
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : TSRC_0
Trigger source 0 initiated this conversion.
0x1 : TSRC_1
Trigger source 1 initiated this conversion.
0x2 : TSRC_2
Corresponding trigger source initiated this conversion.
0x3 : TSRC_3
Corresponding trigger source initiated this conversion.
0x4 : TSRC_4
Corresponding trigger source initiated this conversion.
0x5 : TSRC_5
Corresponding trigger source initiated this conversion.
0x6 : TSRC_6
Corresponding trigger source initiated this conversion.
0x7 : TSRC_7
Corresponding trigger source initiated this conversion.
0x8 : TSRC_8
Corresponding trigger source initiated this conversion.
0x9 : TSRC_9
Corresponding trigger source initiated this conversion.
0xF : TSRC_15
Trigger source 15 initiated this conversion.
End of enumeration elements list.
LOOPCNT : Loop count value
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : LOOPCNT_0
Result is from initial conversion in command.
0x1 : LOOPCNT_1
Result is from second conversion in command.
0x2 : LOOPCNT_2
Result is from LOOPCNT+1 conversion in command.
0x3 : LOOPCNT_3
Result is from LOOPCNT+1 conversion in command.
0x4 : LOOPCNT_4
Result is from LOOPCNT+1 conversion in command.
0x5 : LOOPCNT_5
Result is from LOOPCNT+1 conversion in command.
0x6 : LOOPCNT_6
Result is from LOOPCNT+1 conversion in command.
0x7 : LOOPCNT_7
Result is from LOOPCNT+1 conversion in command.
0x8 : LOOPCNT_8
Result is from LOOPCNT+1 conversion in command.
0x9 : LOOPCNT_9
Result is from LOOPCNT+1 conversion in command.
0xF : LOOPCNT_15
Result is from 16th conversion in command.
End of enumeration elements list.
CMDSRC : Command Buffer Source
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : CMDSRC_0
Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
0x1 : CMDSRC_1
CMD1 buffer used as control settings for this conversion.
0x2 : CMDSRC_2
Corresponding command buffer used as control settings for this conversion.
0x3 : CMDSRC_3
Corresponding command buffer used as control settings for this conversion.
0x4 : CMDSRC_4
Corresponding command buffer used as control settings for this conversion.
0x5 : CMDSRC_5
Corresponding command buffer used as control settings for this conversion.
0x6 : CMDSRC_6
Corresponding command buffer used as control settings for this conversion.
0x7 : CMDSRC_7
Corresponding command buffer used as control settings for this conversion.
0x8 : CMDSRC_8
Corresponding command buffer used as control settings for this conversion.
0x9 : CMDSRC_9
Corresponding command buffer used as control settings for this conversion.
0xF : CMDSRC_15
CMD15 buffer used as control settings for this conversion.
End of enumeration elements list.
VALID : FIFO entry is valid
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : VALID_0
FIFO is empty. Discard any read from RESFIFO.
0x1 : VALID_1
FIFO record read from RESFIFO is valid.
End of enumeration elements list.
Compare Value Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CVL : Compare Value Low.
bits : 0 - 15 (16 bit)
access : read-write
CVH : Compare Value High.
bits : 16 - 31 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x6164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x63F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x66AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x6850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x6BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x6CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x7114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x7148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x757C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x769C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x79E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x7BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x7E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Compare Value Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CVL : Compare Value Low.
bits : 0 - 15 (16 bit)
access : read-write
CVH : Compare Value High.
bits : 16 - 31 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x8150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x82CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x86B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x8744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General A-Side Registers
address_offset : 0x8BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x8C14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Data Result FIFO Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
D : Data result
bits : 0 - 15 (16 bit)
access : read-only
TSRC : Trigger Source
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : TSRC_0
Trigger source 0 initiated this conversion.
0x1 : TSRC_1
Trigger source 1 initiated this conversion.
0x2 : TSRC_2
Corresponding trigger source initiated this conversion.
0x3 : TSRC_3
Corresponding trigger source initiated this conversion.
0x4 : TSRC_4
Corresponding trigger source initiated this conversion.
0x5 : TSRC_5
Corresponding trigger source initiated this conversion.
0x6 : TSRC_6
Corresponding trigger source initiated this conversion.
0x7 : TSRC_7
Corresponding trigger source initiated this conversion.
0x8 : TSRC_8
Corresponding trigger source initiated this conversion.
0x9 : TSRC_9
Corresponding trigger source initiated this conversion.
0xF : TSRC_15
Trigger source 15 initiated this conversion.
End of enumeration elements list.
LOOPCNT : Loop count value
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : LOOPCNT_0
Result is from initial conversion in command.
0x1 : LOOPCNT_1
Result is from second conversion in command.
0x2 : LOOPCNT_2
Result is from LOOPCNT+1 conversion in command.
0x3 : LOOPCNT_3
Result is from LOOPCNT+1 conversion in command.
0x4 : LOOPCNT_4
Result is from LOOPCNT+1 conversion in command.
0x5 : LOOPCNT_5
Result is from LOOPCNT+1 conversion in command.
0x6 : LOOPCNT_6
Result is from LOOPCNT+1 conversion in command.
0x7 : LOOPCNT_7
Result is from LOOPCNT+1 conversion in command.
0x8 : LOOPCNT_8
Result is from LOOPCNT+1 conversion in command.
0x9 : LOOPCNT_9
Result is from LOOPCNT+1 conversion in command.
0xF : LOOPCNT_15
Result is from 16th conversion in command.
End of enumeration elements list.
CMDSRC : Command Buffer Source
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : CMDSRC_0
Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
0x1 : CMDSRC_1
CMD1 buffer used as control settings for this conversion.
0x2 : CMDSRC_2
Corresponding command buffer used as control settings for this conversion.
0x3 : CMDSRC_3
Corresponding command buffer used as control settings for this conversion.
0x4 : CMDSRC_4
Corresponding command buffer used as control settings for this conversion.
0x5 : CMDSRC_5
Corresponding command buffer used as control settings for this conversion.
0x6 : CMDSRC_6
Corresponding command buffer used as control settings for this conversion.
0x7 : CMDSRC_7
Corresponding command buffer used as control settings for this conversion.
0x8 : CMDSRC_8
Corresponding command buffer used as control settings for this conversion.
0x9 : CMDSRC_9
Corresponding command buffer used as control settings for this conversion.
0xF : CMDSRC_15
CMD15 buffer used as control settings for this conversion.
End of enumeration elements list.
VALID : FIFO entry is valid
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : VALID_0
FIFO is empty. Discard any read from RESFIFO.
0x1 : VALID_1
FIFO record read from RESFIFO is valid.
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0x9040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x917C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0x96E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0x9C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Compare Value Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CVL : Compare Value Low.
bits : 0 - 15 (16 bit)
access : read-write
CVH : Compare Value High.
bits : 16 - 31 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0xA1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0xA744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0xACC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0xACC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Calibration General B-Side Registers
address_offset : 0xB240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0xBA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General A-Side Registers
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GAR_VAL : Calibration General A Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
Trigger Control Register
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTEN : Trigger enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HTEN_0
Hardware trigger source disabled
0x1 : HTEN_1
Hardware trigger source enabled
End of enumeration elements list.
FIFO_SEL_A : SAR Result Destination For Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_A_0
Result written to FIFO 0
0x1 : FIFO_SEL_A_1
Result written to FIFO 1
End of enumeration elements list.
FIFO_SEL_B : SAR Result Destination For Channel B
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FIFO_SEL_B_0
Result written to FIFO 0
0x1 : FIFO_SEL_B_1
Result written to FIFO 1
End of enumeration elements list.
TPRI : Trigger priority setting
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : TPRI_0
Set to highest priority, Level 1
0x1 : TPRI_1
Set to corresponding priority level
0x2 : TPRI_2
Set to corresponding priority level
0x3 : TPRI_3
Set to corresponding priority level
0x4 : TPRI_4
Set to corresponding priority level
0x5 : TPRI_5
Set to corresponding priority level
0x6 : TPRI_6
Set to corresponding priority level
0x7 : TPRI_7
Set to corresponding priority level
0x8 : TPRI_8
Set to corresponding priority level
0x9 : TPRI_9
Set to corresponding priority level
0xF : TPRI_15
Set to lowest priority, Level 16
End of enumeration elements list.
RSYNC : Trigger Resync
bits : 15 - 15 (1 bit)
access : read-write
TDLY : Trigger delay select
bits : 16 - 19 (4 bit)
access : read-write
TCMD : Trigger command select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : TCMD_0
Not a valid selection from the command buffer. Trigger event is ignored.
0x1 : TCMD_1
CMD1 is executed
0x2 : TCMD_2
Corresponding CMD is executed
0x3 : TCMD_3
Corresponding CMD is executed
0x4 : TCMD_4
Corresponding CMD is executed
0x5 : TCMD_5
Corresponding CMD is executed
0x6 : TCMD_6
Corresponding CMD is executed
0x7 : TCMD_7
Corresponding CMD is executed
0x8 : TCMD_8
Corresponding CMD is executed
0x9 : TCMD_9
Corresponding CMD is executed
0xF : TCMD_15
CMD15 is executed
End of enumeration elements list.
Calibration General B-Side Registers
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAL_GBR_VAL : Calibration General B Side Register Element
bits : 0 - 15 (16 bit)
access : read-write
ADC Test Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST_LONG : Calibration Sample Time Long
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CST_LONG_0
Normal sample time. Minimum sample time of 3 ADCK cycles.
0x1 : CST_LONG_1
Increased sample time. 67 ADCK cycles total sample time.
End of enumeration elements list.
FOFFM : Force M-side positive offset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FOFFM_0
Normal operation. No forced offset.
0x1 : FOFFM_1
Test configuration. Forced positive offset on MDAC.
End of enumeration elements list.
FOFFP : Force P-side positive offset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : FOFFP_0
Normal operation. No forced offset.
0x1 : FOFFP_1
Test configuration. Forced positive offset on PDAC.
End of enumeration elements list.
FOFFM2 : Force M-side negative offset
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FOFFM2_0
Normal operation. No forced offset.
0x1 : FOFFM2_1
Test configuration. Forced negative offset on MDAC.
End of enumeration elements list.
FOFFP2 : Force P-side negative offset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : FOFFP2_0
Normal operation. No forced offset.
0x1 : FOFFP2_1
Test configuration. Forced negative offset on PDAC.
End of enumeration elements list.
TESTEN : Enable test configuration
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TESTEN_0
Normal operation. Test configuration not enabled.
0x1 : TESTEN_1
Hardware BIST Test in progress.
End of enumeration elements list.
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