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POWERQUAD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x260 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OUTBASE

INABASE

CONTROL

LENGTH

gpreg[6]

CPPRE

MISC

CURSORY

compreg[6]

gpreg[7]

INAFORMAT

gpreg[8]

compreg[7]

gpreg[9]

INBBASE

CORDIC_X

CORDIC_Y

CORDIC_Z

ERRSTAT

gpreg[10]

INTREN

EVENTEN

INTRSTAT

gpreg[11]

INBFORMAT

gpreg[12]

gpreg[13]

gpreg[14]

gpreg[15]

OUTFORMAT

gpreg[0]

compreg[0]

gpreg[1]

compreg[1]

TMPBASE

gpreg[2]

compreg[2]

gpreg[3]

compreg[3]

TMPFORMAT

gpreg[4]

compreg[4]

gpreg[5]

compreg[5]


OUTBASE

Base address register for output region
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTBASE OUTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 outbase

outbase : Base address register for the output region
bits : 0 - 31 (32 bit)
access : read-write


INABASE

Base address register for input A region
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INABASE INABASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 inabase

inabase : Base address register for the input A region
bits : 0 - 31 (32 bit)
access : read-write


CONTROL

PowerQuad Control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 decode_opcode decode_machine inst_busy

decode_opcode : opcode specific to decode_machine
bits : 0 - 3 (4 bit)
access : read-write

decode_machine : 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA
bits : 4 - 7 (4 bit)
access : read-write

inst_busy : Instruction busy signal when high indicates processing is on
bits : 31 - 31 (1 bit)
access : read-only


LENGTH

Length register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENGTH LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 inst_length

inst_length : Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = inst_length[20:16]
bits : 0 - 31 (32 bit)
access : read-write


gpreg[6]

General purpose register bank N.
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[6] gpreg[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


CPPRE

Pre-scale register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPPRE CPPRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cppre_in cppre_out cppre_sat cppre_sat8

cppre_in : co-processor scaling of input
bits : 0 - 7 (8 bit)
access : read-write

cppre_out : co-processor fixed point output
bits : 8 - 15 (8 bit)
access : read-write

cppre_sat : 1 : forces sub-32 bit saturation
bits : 16 - 16 (1 bit)
access : read-write

cppre_sat8 : 0 = 8bits, 1 = 16bits
bits : 17 - 17 (1 bit)
access : read-write


MISC

Misc register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISC MISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 inst_misc

inst_misc : Misc register. For Matrix : Used for scale factor
bits : 0 - 31 (32 bit)
access : read-write


CURSORY

Cursory register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURSORY CURSORY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cursory

cursory : 1 : Enable cursory mode
bits : 0 - 0 (1 bit)
access : read-write


compreg[6]

Compute register bank
address_offset : 0x1254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[6] compreg[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[7]

General purpose register bank N.
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[7] gpreg[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


INAFORMAT

Input A format
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INAFORMAT INAFORMAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ina_formatint ina_formatext ina_scaler

ina_formatint : Input A Internal format (00: q15; 01:q31; 10:float)
bits : 0 - 1 (2 bit)
access : read-write

ina_formatext : Input A External format (00: q15; 01:q31; 10:float)
bits : 4 - 5 (2 bit)
access : read-write

ina_scaler : Input A Scaler value (for scaled 'q31' formats)
bits : 8 - 15 (8 bit)
access : read-write


gpreg[8]

General purpose register bank N.
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[8] gpreg[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[7]

Compute register bank
address_offset : 0x14B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[7] compreg[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[9]

General purpose register bank N.
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[9] gpreg[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


INBBASE

Base address register for input B region
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INBBASE INBBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 inbbase

inbbase : Base address register for the input B region
bits : 0 - 31 (32 bit)
access : read-write


CORDIC_X

Cordic input X register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_X CORDIC_X read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cordic_x

cordic_x : Cordic input x
bits : 0 - 31 (32 bit)
access : read-write


CORDIC_Y

Cordic input Y register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_Y CORDIC_Y read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cordic_y

cordic_y : Cordic input y
bits : 0 - 31 (32 bit)
access : read-write


CORDIC_Z

Cordic input Z register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORDIC_Z CORDIC_Z read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cordic_z

cordic_z : Cordic input z
bits : 0 - 31 (32 bit)
access : read-write


ERRSTAT

Read/Write register where error statuses are captured (sticky)
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRSTAT ERRSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERFLOW NAN FIXEDOVERFLOW UNDERFLOW BUSERROR

OVERFLOW : overflow
bits : 0 - 0 (1 bit)
access : read-write

NAN : nan
bits : 1 - 1 (1 bit)
access : read-write

FIXEDOVERFLOW : fixed_pt_overflow
bits : 2 - 2 (1 bit)
access : read-write

UNDERFLOW : underflow
bits : 3 - 3 (1 bit)
access : read-write

BUSERROR : bus_error
bits : 4 - 4 (1 bit)
access : read-write


gpreg[10]

General purpose register bank N.
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[10] gpreg[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


INTREN

INTERRUPT enable register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTREN INTREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 intr_oflow intr_nan intr_fixed intr_uflow intr_berr intr_comp

intr_oflow : 1 : Enable interrupt on Floating point overflow
bits : 0 - 0 (1 bit)
access : read-write

intr_nan : 1 : Enable interrupt on Floating point NaN
bits : 1 - 1 (1 bit)
access : read-write

intr_fixed : 1: Enable interrupt on Fixed point Overflow
bits : 2 - 2 (1 bit)
access : read-write

intr_uflow : 1 : Enable interrupt on Subnormal truncation
bits : 3 - 3 (1 bit)
access : read-write

intr_berr : 1: Enable interrupt on AHBM Buss Error
bits : 4 - 4 (1 bit)
access : read-write

intr_comp : 1: Enable interrupt on instruction completion
bits : 7 - 7 (1 bit)
access : read-write


EVENTEN

Event Enable register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTEN EVENTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 event_oflow event_nan event_fixed event_uflow event_berr event_comp

event_oflow : 1 : Enable event trigger on Floating point overflow
bits : 0 - 0 (1 bit)
access : read-write

event_nan : 1 : Enable event trigger on Floating point NaN
bits : 1 - 1 (1 bit)
access : read-write

event_fixed : 1: Enable event trigger on Fixed point Overflow
bits : 2 - 2 (1 bit)
access : read-write

event_uflow : 1 : Enable event trigger on Subnormal truncation
bits : 3 - 3 (1 bit)
access : read-write

event_berr : 1: Enable event trigger on AHBM Buss Error
bits : 4 - 4 (1 bit)
access : read-write

event_comp : 1: Enable event trigger on instruction completion
bits : 7 - 7 (1 bit)
access : read-write


INTRSTAT

INTERRUPT STATUS register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTRSTAT INTRSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 intr_stat

intr_stat : Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit
bits : 0 - 0 (1 bit)
access : read-write


gpreg[11]

General purpose register bank N.
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[11] gpreg[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


INBFORMAT

Input B format
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INBFORMAT INBFORMAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 inb_formatint inb_formatext inb_scaler

inb_formatint : Input B Internal format (00: q15; 01:q31; 10:float)
bits : 0 - 1 (2 bit)
access : read-write

inb_formatext : Input B External format (00: q15; 01:q31; 10:float)
bits : 4 - 5 (2 bit)
access : read-write

inb_scaler : Input B Scaler value (for scaled 'q31' formats)
bits : 8 - 15 (8 bit)
access : read-write


gpreg[12]

General purpose register bank N.
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[12] gpreg[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[13]

General purpose register bank N.
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[13] gpreg[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[14]

General purpose register bank N.
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[14] gpreg[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[15]

General purpose register bank N.
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[15] gpreg[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


OUTFORMAT

Output format
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTFORMAT OUTFORMAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 out_formatint out_formatext out_scaler

out_formatint : Output Internal format (00: q15; 01:q31; 10:float)
bits : 0 - 1 (2 bit)
access : read-write

out_formatext : Output External format (00: q15; 01:q31; 10:float)
bits : 4 - 5 (2 bit)
access : read-write

out_scaler : Output Scaler value (for scaled 'q31' formats)
bits : 8 - 15 (8 bit)
access : read-write


gpreg[0]

General purpose register bank N.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[0] gpreg[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[0]

Compute register bank
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[0] compreg[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[1]

General purpose register bank N.
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[1] gpreg[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[1]

Compute register bank
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[1] compreg[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


TMPBASE

Base address register for temp region
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPBASE TMPBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tmpbase

tmpbase : Base address register for the temporary region
bits : 0 - 31 (32 bit)
access : read-write


gpreg[2]

General purpose register bank N.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[2] gpreg[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[2]

Compute register bank
address_offset : 0x90C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[2] compreg[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[3]

General purpose register bank N.
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[3] gpreg[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[3]

Compute register bank
address_offset : 0xB58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[3] compreg[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


TMPFORMAT

Temp format
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPFORMAT TMPFORMAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tmp_formatint tmp_formatext tmp_scaler

tmp_formatint : Temp Internal format (00: q15; 01:q31; 10:float)
bits : 0 - 1 (2 bit)
access : read-write

tmp_formatext : Temp External format (00: q15; 01:q31; 10:float)
bits : 4 - 5 (2 bit)
access : read-write

tmp_scaler : Temp Scaler value (for scaled 'q31' formats)
bits : 8 - 15 (8 bit)
access : read-write


gpreg[4]

General purpose register bank N.
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[4] gpreg[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[4]

Compute register bank
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[4] compreg[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write


gpreg[5]

General purpose register bank N.
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

gpreg[5] gpreg[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpreg

gpreg : General purpose register bank
bits : 0 - 31 (32 bit)
access : read-write


compreg[5]

Compute register bank
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

compreg[5] compreg[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compreg

compreg : Compute register bank
bits : 0 - 31 (32 bit)
access : read-write



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