\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TR

PRER

WUTR

CR

PRIVCR

SMCR

WPR

CALR

SHIFTR

TSTR

TSDR

TSSSR

DR

ALRMAR

ALRMASSR

ALRMBR

ALRMBSSR

SR

MISR

SMISR

SCR

SSR

ICSR


TR

time register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : Second units in BCD format
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)


PRER

prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER PRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV_S PREDIV_A

PREDIV_S : Synchronous prescaler factor
bits : 0 - 14 (15 bit)

PREDIV_A : Asynchronous prescaler factor
bits : 16 - 22 (7 bit)


WUTR

wakeup timer register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WUTR WUTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUT WUTOCLR

WUT : Wakeup auto-reload value bits
bits : 0 - 15 (16 bit)

WUTOCLR : WUTOCLR
bits : 16 - 31 (16 bit)


CR

RTC control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUCKSEL TSEDGE REFCKON BYPSHAD FMT ALRAE ALRBE WUTE TSE ALRAIE ALRBIE WUTIE TSIE ADD1H SUB1H BKP COSEL POL OSEL COE ITSE TAMPTS TAMPOE TAMPALRM_PU TAMPALRM_TYPE OUT2EN

WUCKSEL : WUCKSEL
bits : 0 - 2 (3 bit)

TSEDGE : TSEDGE
bits : 3 - 3 (1 bit)

REFCKON : REFCKON
bits : 4 - 4 (1 bit)

BYPSHAD : BYPSHAD
bits : 5 - 5 (1 bit)

FMT : FMT
bits : 6 - 6 (1 bit)

ALRAE : ALRAE
bits : 8 - 8 (1 bit)

ALRBE : ALRBE
bits : 9 - 9 (1 bit)

WUTE : WUTE
bits : 10 - 10 (1 bit)

TSE : TSE
bits : 11 - 11 (1 bit)

ALRAIE : ALRAIE
bits : 12 - 12 (1 bit)

ALRBIE : ALRBIE
bits : 13 - 13 (1 bit)

WUTIE : WUTIE
bits : 14 - 14 (1 bit)

TSIE : TSIE
bits : 15 - 15 (1 bit)

ADD1H : ADD1H
bits : 16 - 16 (1 bit)

SUB1H : SUB1H
bits : 17 - 17 (1 bit)

BKP : BKP
bits : 18 - 18 (1 bit)

COSEL : COSEL
bits : 19 - 19 (1 bit)

POL : POL
bits : 20 - 20 (1 bit)

OSEL : OSEL
bits : 21 - 22 (2 bit)

COE : COE
bits : 23 - 23 (1 bit)

ITSE : ITSE
bits : 24 - 24 (1 bit)

TAMPTS : TAMPTS
bits : 25 - 25 (1 bit)

TAMPOE : TAMPOE
bits : 26 - 26 (1 bit)

TAMPALRM_PU : TAMPALRM_PU
bits : 29 - 29 (1 bit)

TAMPALRM_TYPE : TAMPALRM_TYPE
bits : 30 - 30 (1 bit)

OUT2EN : OUT2EN
bits : 31 - 31 (1 bit)


PRIVCR

RTC privilege mode control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIVCR PRIVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAPRIV ALRBPRIV WUTPRIV TSPRIV CALPRIV INITPRIV PRIV

ALRAPRIV : ALRAPRIV
bits : 0 - 0 (1 bit)

ALRBPRIV : ALRBPRIV
bits : 1 - 1 (1 bit)

WUTPRIV : WUTPRIV
bits : 2 - 2 (1 bit)

TSPRIV : TSPRIV
bits : 3 - 3 (1 bit)

CALPRIV : CALPRIV
bits : 13 - 13 (1 bit)

INITPRIV : INITPRIV
bits : 14 - 14 (1 bit)

PRIV : PRIV
bits : 15 - 15 (1 bit)


SMCR

RTC secure mode control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCR SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRADPROT ALRBDPROT WUTDPROT TSDPROT CALDPROT INITDPROT DECPROT

ALRADPROT : ALRADPROT
bits : 0 - 0 (1 bit)

ALRBDPROT : ALRBDPROT
bits : 1 - 1 (1 bit)

WUTDPROT : WUTDPROT
bits : 2 - 2 (1 bit)

TSDPROT : TSDPROT
bits : 3 - 3 (1 bit)

CALDPROT : CALDPROT
bits : 13 - 13 (1 bit)

INITDPROT : INITDPROT
bits : 14 - 14 (1 bit)

DECPROT : DECPROT
bits : 15 - 15 (1 bit)


WPR

write protection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Write protection key
bits : 0 - 7 (8 bit)


CALR

calibration register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALR CALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALM LPCAL CALW16 CALW8 CALP

CALM : Calibration minus
bits : 0 - 8 (9 bit)

LPCAL : LPCAL
bits : 12 - 12 (1 bit)

CALW16 : Use a 16-second calibration cycle period
bits : 13 - 13 (1 bit)

CALW8 : Use an 8-second calibration cycle period
bits : 14 - 14 (1 bit)

CALP : Increase frequency of RTC by 488.5 ppm
bits : 15 - 15 (1 bit)


SHIFTR

shift control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SHIFTR SHIFTR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBFS ADD1S

SUBFS : Subtract a fraction of a second
bits : 0 - 14 (15 bit)

ADD1S : Add one second
bits : 31 - 31 (1 bit)


TSTR

time stamp time register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSTR TSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : Second units in BCD format
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)


TSDR

time stamp date register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSDR TSDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU

DU : Date units in BCD format
bits : 0 - 3 (4 bit)

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)

MU : Month units in BCD format
bits : 8 - 11 (4 bit)

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)

WDU : Week day units
bits : 13 - 15 (3 bit)


TSSSR

timestamp sub second register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSSSR TSSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : Sub second value
bits : 0 - 15 (16 bit)


DR

date register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU YU YT

DU : Date units in BCD format
bits : 0 - 3 (4 bit)

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)

MU : Month units in BCD format
bits : 8 - 11 (4 bit)

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)

WDU : Week day units
bits : 13 - 15 (3 bit)

YU : Year units in BCD format
bits : 16 - 19 (4 bit)

YT : Year tens in BCD format
bits : 20 - 23 (4 bit)


ALRMAR

alarm A register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMAR ALRMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MSK1 MNU MNT MSK2 HU HT PM MSK3 DU DT WDSEL MSK4

SU : Second units in BCD format
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)

MSK1 : Alarm A seconds mask
bits : 7 - 7 (1 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

MSK2 : Alarm A minutes mask
bits : 15 - 15 (1 bit)

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)

MSK3 : Alarm A hours mask
bits : 23 - 23 (1 bit)

DU : Date units or day in BCD format
bits : 24 - 27 (4 bit)

DT : Date tens in BCD format
bits : 28 - 29 (2 bit)

WDSEL : Week day selection
bits : 30 - 30 (1 bit)

MSK4 : Alarm A date mask
bits : 31 - 31 (1 bit)


ALRMASSR

alarm A sub second register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMASSR ALRMASSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS MASKSS

SS : Sub seconds value
bits : 0 - 14 (15 bit)

MASKSS : Mask the most-significant bits starting at this bit
bits : 24 - 27 (4 bit)


ALRMBR

alarm B register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMBR ALRMBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MSK1 MNU MNT MSK2 HU HT PM MSK3 DU DT WDSEL MSK4

SU : Second units in BCD format
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)

MSK1 : Alarm B seconds mask
bits : 7 - 7 (1 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

MSK2 : Alarm B minutes mask
bits : 15 - 15 (1 bit)

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)

MSK3 : Alarm B hours mask
bits : 23 - 23 (1 bit)

DU : Date units or day in BCD format
bits : 24 - 27 (4 bit)

DT : Date tens in BCD format
bits : 28 - 29 (2 bit)

WDSEL : Week day selection
bits : 30 - 30 (1 bit)

MSK4 : Alarm B date mask
bits : 31 - 31 (1 bit)


ALRMBSSR

alarm B sub second register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMBSSR ALRMBSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS MASKSS

SS : Sub seconds value
bits : 0 - 14 (15 bit)

MASKSS : Mask the most-significant bits starting at this bit
bits : 24 - 27 (4 bit)


SR

RTC status register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAF ALRBF WUTF TSF TSOVF ITSF

ALRAF : ALRAF
bits : 0 - 0 (1 bit)

ALRBF : ALRBF
bits : 1 - 1 (1 bit)

WUTF : WUTF
bits : 2 - 2 (1 bit)

TSF : TSF
bits : 3 - 3 (1 bit)

TSOVF : TSOVF
bits : 4 - 4 (1 bit)

ITSF : ITSF
bits : 5 - 5 (1 bit)


MISR

RTC non-secure masked interrupt status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MISR MISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAMF ALRBMF WUTMF TSMF TSOVMF ITSMF

ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)

ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)

WUTMF : WUTMF
bits : 2 - 2 (1 bit)

TSMF : TSMF
bits : 3 - 3 (1 bit)

TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)

ITSMF : ITSMF
bits : 5 - 5 (1 bit)


SMISR

RTC secure masked interrupt status register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SMISR SMISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAMF ALRBMF WUTMF TSMF TSOVMF ITSMF

ALRAMF : ALRAMF
bits : 0 - 0 (1 bit)

ALRBMF : ALRBMF
bits : 1 - 1 (1 bit)

WUTMF : WUTMF
bits : 2 - 2 (1 bit)

TSMF : TSMF
bits : 3 - 3 (1 bit)

TSOVMF : TSOVMF
bits : 4 - 4 (1 bit)

ITSMF : ITSMF
bits : 5 - 5 (1 bit)


SCR

RTC status clear register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRAF CALRBF CWUTF CTSF CTSOVF CITSF

CALRAF : CALRAF
bits : 0 - 0 (1 bit)

CALRBF : CALRBF
bits : 1 - 1 (1 bit)

CWUTF : CWUTF
bits : 2 - 2 (1 bit)

CTSF : CTSF
bits : 3 - 3 (1 bit)

CTSOVF : CTSOVF
bits : 4 - 4 (1 bit)

CITSF : CITSF
bits : 5 - 5 (1 bit)


SSR

RTC sub second register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSR SSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : SS
bits : 0 - 15 (16 bit)


ICSR

RTC initialization control and status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAWF ALRBWF WUTWF SHPF INITS RSF INITF INIT RECALPF

ALRAWF : Alarm A write flag
bits : 0 - 0 (1 bit)
access : read-only

ALRBWF : Alarm B write flag
bits : 1 - 1 (1 bit)
access : read-only

WUTWF : Wakeup timer write flag
bits : 2 - 2 (1 bit)
access : read-only

SHPF : Shift operation pending
bits : 3 - 3 (1 bit)
access : read-write

INITS : Initialization status flag
bits : 4 - 4 (1 bit)
access : read-only

RSF : Registers synchronization flag
bits : 5 - 5 (1 bit)
access : read-write

INITF : Initialization flag
bits : 6 - 6 (1 bit)
access : read-only

INIT : Initialization mode
bits : 7 - 7 (1 bit)
access : read-write

RECALPF : Recalibration pending Flag
bits : 16 - 16 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.