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SDIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CLKENA

CARDTHRCTL

BACKENDPWR

FIFO[6]

RESP[3]

FIFO[7]

TMOUT

FIFO[8]

FIFO[9]

CTYPE

FIFO[10]

FIFO[11]

BLKSIZ

FIFO[12]

FIFO[13]

BYTCNT

FIFO[14]

FIFO[15]

INTMASK

FIFO[16]

CMDARG

FIFO[17]

FIFO[18]

CMD

FIFO[19]

FIFO[20]

FIFO[21]

FIFO[22]

FIFO[23]

FIFO[24]

FIFO[25]

FIFO[26]

FIFO[27]

PWREN

MINTSTS

FIFO[0]

FIFO[28]

RINTSTS

FIFO[29]

FIFO[30]

STATUS

FIFO[31]

FIFOTH

FIFO[32]

FIFO[33]

CDETECT

FIFO[34]

FIFO[35]

WRTPRT

FIFO[36]

FIFO[37]

FIFO[38]

TCBCNT

FIFO[39]

RESP[0]

TBBCNT

FIFO[1]

FIFO[40]

FIFO[41]

DEBNCE

FIFO[42]

FIFO[43]

FIFO[44]

FIFO[45]

FIFO[46]

FIFO[47]

FIFO[48]

RST_N

FIFO[49]

FIFO[50]

FIFO[51]

CLKDIV

BMOD

FIFO[2]

FIFO[52]

PLDMND

FIFO[53]

FIFO[54]

DBADDR

FIFO[55]

IDSTS

FIFO[56]

FIFO[57]

IDINTEN

FIFO[58]

RESP[1]

DSCADDR

FIFO[59]

BUFADDR

FIFO[60]

FIFO[61]

FIFO[62]

FIFO[3]

FIFO[63]

FIFO[4]

RESP[2]

FIFO[5]


CTRL

Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTROLLER_RESET FIFO_RESET DMA_RESET INT_ENABLE READ_WAIT SEND_IRQ_RESPONSE ABORT_READ_DATA SEND_CCSD SEND_AUTO_STOP_CCSD CEATA_DEVICE_INTERRUPT_STATUS CARD_VOLTAGE_A0 CARD_VOLTAGE_A1 CARD_VOLTAGE_A2 USE_INTERNAL_DMAC

CONTROLLER_RESET : Controller reset.
bits : 0 - 0 (1 bit)
access : read-write

FIFO_RESET : Fifo reset.
bits : 1 - 1 (1 bit)
access : read-write

DMA_RESET : DMA reset.
bits : 2 - 2 (1 bit)
access : read-write

INT_ENABLE : Global interrupt enable/disable bit.
bits : 4 - 4 (1 bit)
access : read-write

READ_WAIT : Read/wait.
bits : 6 - 6 (1 bit)
access : read-write

SEND_IRQ_RESPONSE : Send irq response.
bits : 7 - 7 (1 bit)
access : read-write

ABORT_READ_DATA : Abort read data.
bits : 8 - 8 (1 bit)
access : read-write

SEND_CCSD : Send ccsd.
bits : 9 - 9 (1 bit)
access : read-write

SEND_AUTO_STOP_CCSD : Send auto stop ccsd.
bits : 10 - 10 (1 bit)
access : read-write

CEATA_DEVICE_INTERRUPT_STATUS : CEATA device interrupt status.
bits : 11 - 11 (1 bit)
access : read-write

CARD_VOLTAGE_A0 : Controls the state of the SD_VOLT0 pin.
bits : 16 - 16 (1 bit)
access : read-write

CARD_VOLTAGE_A1 : Controls the state of the SD_VOLT1 pin.
bits : 17 - 17 (1 bit)
access : read-write

CARD_VOLTAGE_A2 : Controls the state of the SD_VOLT2 pin.
bits : 18 - 18 (1 bit)
access : read-write

USE_INTERNAL_DMAC : SD/MMC DMA use.
bits : 25 - 25 (1 bit)
access : read-write


CLKENA

Clock Enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKENA CLKENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCLK0_ENABLE CCLK1_ENABLE CCLK0_LOW_POWER CCLK1_LOW_POWER

CCLK0_ENABLE : Clock-enable control for SD card 0 clock.
bits : 0 - 0 (1 bit)
access : read-write

CCLK1_ENABLE : Clock-enable control for SD card 1 clock.
bits : 1 - 1 (1 bit)
access : read-write

CCLK0_LOW_POWER : Low-power control for SD card 0 clock.
bits : 16 - 16 (1 bit)
access : read-write

CCLK1_LOW_POWER : Low-power control for SD card 1 clock.
bits : 17 - 17 (1 bit)
access : read-write


CARDTHRCTL

Card Threshold Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CARDTHRCTL CARDTHRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDRDTHREN BSYCLRINTEN CARDTHRESHOLD

CARDRDTHREN : Card Read Threshold Enable.
bits : 0 - 0 (1 bit)
access : read-write

BSYCLRINTEN : Busy Clear Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-write

CARDTHRESHOLD : Card Threshold size.
bits : 16 - 23 (8 bit)
access : read-write


BACKENDPWR

Power control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BACKENDPWR BACKENDPWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BACKENDPWR

BACKENDPWR : Back-end Power control for card application.
bits : 0 - 0 (1 bit)
access : read-write


FIFO[6]

SDIF FIFO
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[6] FIFO[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RESP[3]

Response register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[3] RESP[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE

RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[7]

SDIF FIFO
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[7] FIFO[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


TMOUT

Time-out register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMOUT TMOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE_TIMEOUT DATA_TIMEOUT

RESPONSE_TIMEOUT : Response time-out value.
bits : 0 - 7 (8 bit)
access : read-write

DATA_TIMEOUT : Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
bits : 8 - 31 (24 bit)
access : read-write


FIFO[8]

SDIF FIFO
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[8] FIFO[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[9]

SDIF FIFO
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[9] FIFO[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


CTYPE

Card Type register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTYPE CTYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARD0_WIDTH0 CARD1_WIDTH0 CARD0_WIDTH1 CARD1_WIDTH1

CARD0_WIDTH0 : Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set to 0).
bits : 0 - 0 (1 bit)
access : read-write

CARD1_WIDTH0 : Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set to 0).
bits : 1 - 1 (1 bit)
access : read-write

CARD0_WIDTH1 : Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
bits : 16 - 16 (1 bit)
access : read-write

CARD1_WIDTH1 : Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
bits : 17 - 17 (1 bit)
access : read-write


FIFO[10]

SDIF FIFO
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[10] FIFO[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[11]

SDIF FIFO
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[11] FIFO[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


BLKSIZ

Block Size register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLKSIZ BLKSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK_SIZE

BLOCK_SIZE : Block size.
bits : 0 - 15 (16 bit)
access : read-write


FIFO[12]

SDIF FIFO
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[12] FIFO[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[13]

SDIF FIFO
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[13] FIFO[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


BYTCNT

Byte Count register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BYTCNT BYTCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTE_COUNT

BYTE_COUNT : Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[14]

SDIF FIFO
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[14] FIFO[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[15]

SDIF FIFO
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[15] FIFO[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


INTMASK

Interrupt Mask register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTMASK INTMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDET RE CDONE DTO TXDR RXDR RCRC DCRC RTO DRTO HTO FRUN HLE SBE ACD EBE SDIO_INT_MASK

CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write

RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write

CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write

DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write

TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write

RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write

RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write

DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write

RTO : Response time-out.
bits : 8 - 8 (1 bit)
access : read-write

DRTO : Data read time-out.
bits : 9 - 9 (1 bit)
access : read-write

HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write

FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write

HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write

SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write

ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write

EBE : End-bit error (read)/Write no CRC.
bits : 15 - 15 (1 bit)
access : read-write

SDIO_INT_MASK : Mask SDIO interrupt.
bits : 16 - 16 (1 bit)
access : read-write


FIFO[16]

SDIF FIFO
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[16] FIFO[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


CMDARG

Command Argument register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMDARG CMDARG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ARG

CMD_ARG : Value indicates command argument to be passed to card.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[17]

SDIF FIFO
address_offset : 0x2864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[17] FIFO[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[18]

SDIF FIFO
address_offset : 0x2AAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[18] FIFO[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


CMD

Command register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_INDEX RESPONSE_EXPECT RESPONSE_LENGTH CHECK_RESPONSE_CRC DATA_EXPECTED READ_WRITE TRANSFER_MODE SEND_AUTO_STOP WAIT_PRVDATA_COMPLETE STOP_ABORT_CMD SEND_INITIALIZATION CARD_NUMBER UPDATE_CLOCK_REGISTERS_ONLY READ_CEATA_DEVICE CCS_EXPECTED ENABLE_BOOT EXPECT_BOOT_ACK DISABLE_BOOT BOOT_MODE VOLT_SWITCH USE_HOLD_REG START_CMD

CMD_INDEX : Command index.
bits : 0 - 5 (6 bit)
access : read-write

RESPONSE_EXPECT : Response expect.
bits : 6 - 6 (1 bit)
access : read-write

RESPONSE_LENGTH : Response length.
bits : 7 - 7 (1 bit)
access : read-write

CHECK_RESPONSE_CRC : Check response CRC.
bits : 8 - 8 (1 bit)
access : read-write

DATA_EXPECTED : Data expected.
bits : 9 - 9 (1 bit)
access : read-write

READ_WRITE : read/write.
bits : 10 - 10 (1 bit)
access : read-write

TRANSFER_MODE : Transfer mode.
bits : 11 - 11 (1 bit)
access : read-write

SEND_AUTO_STOP : Send auto stop.
bits : 12 - 12 (1 bit)
access : read-write

WAIT_PRVDATA_COMPLETE : Wait prvdata complete.
bits : 13 - 13 (1 bit)
access : read-write

STOP_ABORT_CMD : Stop abort command.
bits : 14 - 14 (1 bit)
access : read-write

SEND_INITIALIZATION : Send initialization.
bits : 15 - 15 (1 bit)
access : read-write

CARD_NUMBER : Specifies the card number of SDCARD for which the current Command is being executed
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

0 : CARD0

Command will be execute on SDCARD 0

0x1 : CARD1

Command will be execute on SDCARD 1

End of enumeration elements list.

UPDATE_CLOCK_REGISTERS_ONLY : Update clock registers only.
bits : 21 - 21 (1 bit)
access : read-write

READ_CEATA_DEVICE : Read ceata device.
bits : 22 - 22 (1 bit)
access : read-write

CCS_EXPECTED : CCS expected.
bits : 23 - 23 (1 bit)
access : read-write

ENABLE_BOOT : Enable Boot - this bit should be set only for mandatory boot mode.
bits : 24 - 24 (1 bit)
access : read-write

EXPECT_BOOT_ACK : Expect Boot Acknowledge.
bits : 25 - 25 (1 bit)
access : read-write

DISABLE_BOOT : Disable Boot.
bits : 26 - 26 (1 bit)
access : read-write

BOOT_MODE : Boot Mode.
bits : 27 - 27 (1 bit)
access : read-write

VOLT_SWITCH : Voltage switch bit.
bits : 28 - 28 (1 bit)
access : read-write

USE_HOLD_REG : Use Hold Register.
bits : 29 - 29 (1 bit)
access : read-write

START_CMD : Start command.
bits : 31 - 31 (1 bit)
access : read-write


FIFO[19]

SDIF FIFO
address_offset : 0x2CF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[19] FIFO[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[20]

SDIF FIFO
address_offset : 0x2F48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[20] FIFO[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[21]

SDIF FIFO
address_offset : 0x319C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[21] FIFO[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[22]

SDIF FIFO
address_offset : 0x33F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[22] FIFO[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[23]

SDIF FIFO
address_offset : 0x3650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[23] FIFO[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[24]

SDIF FIFO
address_offset : 0x38B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[24] FIFO[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[25]

SDIF FIFO
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[25] FIFO[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[26]

SDIF FIFO
address_offset : 0x3D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[26] FIFO[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[27]

SDIF FIFO
address_offset : 0x3FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[27] FIFO[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


PWREN

Power Enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWREN PWREN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWER_ENABLE0 POWER_ENABLE1

POWER_ENABLE0 : Power on/off switch for card 0; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 0.
bits : 0 - 0 (1 bit)
access : read-write

POWER_ENABLE1 : Power on/off switch for card 1; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card 1.
bits : 1 - 1 (1 bit)
access : read-write


MINTSTS

Masked Interrupt Status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MINTSTS MINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDET RE CDONE DTO TXDR RXDR RCRC DCRC RTO DRTO HTO FRUN HLE SBE ACD EBE SDIO_INTERRUPT

CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write

RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write

CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write

DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write

TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write

RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write

RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write

DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write

RTO : Response time-out.
bits : 8 - 8 (1 bit)
access : read-write

DRTO : Data read time-out.
bits : 9 - 9 (1 bit)
access : read-write

HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write

FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write

HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write

SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write

ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write

EBE : End-bit error (read)/write no CRC.
bits : 15 - 15 (1 bit)
access : read-write

SDIO_INTERRUPT : Interrupt from SDIO card.
bits : 16 - 16 (1 bit)
access : read-write


FIFO[0]

SDIF FIFO
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[0] FIFO[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[28]

SDIF FIFO
address_offset : 0x4258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[28] FIFO[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RINTSTS

Raw Interrupt Status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RINTSTS RINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDET RE CDONE DTO TXDR RXDR RCRC DCRC RTO_BAR DRTO_BDS HTO FRUN HLE SBE ACD EBE SDIO_INTERRUPT

CDET : Card detect.
bits : 0 - 0 (1 bit)
access : read-write

RE : Response error.
bits : 1 - 1 (1 bit)
access : read-write

CDONE : Command done.
bits : 2 - 2 (1 bit)
access : read-write

DTO : Data transfer over.
bits : 3 - 3 (1 bit)
access : read-write

TXDR : Transmit FIFO data request.
bits : 4 - 4 (1 bit)
access : read-write

RXDR : Receive FIFO data request.
bits : 5 - 5 (1 bit)
access : read-write

RCRC : Response CRC error.
bits : 6 - 6 (1 bit)
access : read-write

DCRC : Data CRC error.
bits : 7 - 7 (1 bit)
access : read-write

RTO_BAR : Response time-out (RTO)/Boot Ack Received (BAR).
bits : 8 - 8 (1 bit)
access : read-write

DRTO_BDS : Data read time-out (DRTO)/Boot Data Start (BDS).
bits : 9 - 9 (1 bit)
access : read-write

HTO : Data starvation-by-host time-out (HTO).
bits : 10 - 10 (1 bit)
access : read-write

FRUN : FIFO underrun/overrun error.
bits : 11 - 11 (1 bit)
access : read-write

HLE : Hardware locked write error.
bits : 12 - 12 (1 bit)
access : read-write

SBE : Start-bit error.
bits : 13 - 13 (1 bit)
access : read-write

ACD : Auto command done.
bits : 14 - 14 (1 bit)
access : read-write

EBE : End-bit error (read)/write no CRC.
bits : 15 - 15 (1 bit)
access : read-write

SDIO_INTERRUPT : Interrupt from SDIO card.
bits : 16 - 16 (1 bit)
access : read-write


FIFO[29]

SDIF FIFO
address_offset : 0x44CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[29] FIFO[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[30]

SDIF FIFO
address_offset : 0x4744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[30] FIFO[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


STATUS

Status register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_RX_WATERMARK FIFO_TX_WATERMARK FIFO_EMPTY FIFO_FULL CMDFSMSTATES DATA_3_STATUS DATA_BUSY DATA_STATE_MC_BUSY RESPONSE_INDEX FIFO_COUNT DMA_ACK DMA_REQ

FIFO_RX_WATERMARK : FIFO reached Receive watermark level; not qualified with data transfer.
bits : 0 - 0 (1 bit)
access : read-write

FIFO_TX_WATERMARK : FIFO reached Transmit watermark level; not qualified with data transfer.
bits : 1 - 1 (1 bit)
access : read-write

FIFO_EMPTY : FIFO is empty status.
bits : 2 - 2 (1 bit)
access : read-write

FIFO_FULL : FIFO is full status.
bits : 3 - 3 (1 bit)
access : read-write

CMDFSMSTATES : Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits.
bits : 4 - 7 (4 bit)
access : read-write

DATA_3_STATUS : Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
bits : 8 - 8 (1 bit)
access : read-write

DATA_BUSY : Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
bits : 9 - 9 (1 bit)
access : read-write

DATA_STATE_MC_BUSY : Data transmit or receive state-machine is busy.
bits : 10 - 10 (1 bit)
access : read-write

RESPONSE_INDEX : Index of previous response, including any auto-stop sent by core.
bits : 11 - 16 (6 bit)
access : read-write

FIFO_COUNT : FIFO count - Number of filled locations in FIFO.
bits : 17 - 29 (13 bit)
access : read-write

DMA_ACK : DMA acknowledge signal state.
bits : 30 - 30 (1 bit)
access : read-write

DMA_REQ : DMA request signal state.
bits : 31 - 31 (1 bit)
access : read-write


FIFO[31]

SDIF FIFO
address_offset : 0x49C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[31] FIFO[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFOTH

FIFO Threshold Watermark register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOTH FIFOTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_WMARK RX_WMARK DMA_MTS

TX_WMARK : FIFO threshold watermark level when transmitting data to card.
bits : 0 - 11 (12 bit)
access : read-write

RX_WMARK : FIFO threshold watermark level when receiving data to card.
bits : 16 - 27 (12 bit)
access : read-write

DMA_MTS : Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.
bits : 28 - 30 (3 bit)
access : read-write


FIFO[32]

SDIF FIFO
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[32] FIFO[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[33]

SDIF FIFO
address_offset : 0x4EC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[33] FIFO[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


CDETECT

Card Detect register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDETECT CDETECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARD0_DETECT CARD1_DETECT

CARD0_DETECT : Card 0 detect
bits : 0 - 0 (1 bit)
access : read-write

CARD1_DETECT : Card 1 detect
bits : 1 - 1 (1 bit)
access : read-write


FIFO[34]

SDIF FIFO
address_offset : 0x514C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[34] FIFO[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[35]

SDIF FIFO
address_offset : 0x53D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[35] FIFO[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


WRTPRT

Write Protect register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRTPRT WRTPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRITE_PROTECT

WRITE_PROTECT : Write protect.
bits : 0 - 0 (1 bit)
access : read-write


FIFO[36]

SDIF FIFO
address_offset : 0x5668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[36] FIFO[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[37]

SDIF FIFO
address_offset : 0x58FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[37] FIFO[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[38]

SDIF FIFO
address_offset : 0x5B94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[38] FIFO[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


TCBCNT

Transferred CIU Card Byte Count register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCBCNT TCBCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANS_CARD_BYTE_COUNT

TRANS_CARD_BYTE_COUNT : Number of bytes transferred by CIU unit to card.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[39]

SDIF FIFO
address_offset : 0x5E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[39] FIFO[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RESP[0]

Response register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[0] RESP[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE

RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write


TBBCNT

Transferred Host to BIU-FIFO Byte Count register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBBCNT TBBCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANS_FIFO_BYTE_COUNT

TRANS_FIFO_BYTE_COUNT : Number of bytes transferred between Host/DMA memory and BIU FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[1]

SDIF FIFO
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[1] FIFO[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[40]

SDIF FIFO
address_offset : 0x60D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[40] FIFO[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[41]

SDIF FIFO
address_offset : 0x6374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[41] FIFO[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


DEBNCE

Debounce Count register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBNCE DEBNCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBOUNCE_COUNT

DEBOUNCE_COUNT : Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
bits : 0 - 23 (24 bit)
access : read-write


FIFO[42]

SDIF FIFO
address_offset : 0x661C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[42] FIFO[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[43]

SDIF FIFO
address_offset : 0x68C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[43] FIFO[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[44]

SDIF FIFO
address_offset : 0x6B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[44] FIFO[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[45]

SDIF FIFO
address_offset : 0x6E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[45] FIFO[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[46]

SDIF FIFO
address_offset : 0x70E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[46] FIFO[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[47]

SDIF FIFO
address_offset : 0x73A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[47] FIFO[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[48]

SDIF FIFO
address_offset : 0x7660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[48] FIFO[48] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RST_N

Hardware Reset
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST_N RST_N read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARD_RESET

CARD_RESET : Hardware reset.
bits : 0 - 0 (1 bit)
access : read-write


FIFO[49]

SDIF FIFO
address_offset : 0x7924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[49] FIFO[49] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[50]

SDIF FIFO
address_offset : 0x7BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[50] FIFO[50] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[51]

SDIF FIFO
address_offset : 0x7EB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[51] FIFO[51] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


CLKDIV

Clock Divider register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_DIVIDER0

CLK_DIVIDER0 : Clock divider-0 value.
bits : 0 - 7 (8 bit)
access : read-write


BMOD

Bus Mode register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMOD BMOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR FB DSL DE PBL

SWR : Software Reset.
bits : 0 - 0 (1 bit)
access : read-write

FB : Fixed Burst.
bits : 1 - 1 (1 bit)
access : read-write

DSL : Descriptor Skip Length.
bits : 2 - 6 (5 bit)
access : read-write

DE : SD/MMC DMA Enable.
bits : 7 - 7 (1 bit)
access : read-write

PBL : Programmable Burst Length.
bits : 8 - 10 (3 bit)
access : read-write


FIFO[2]

SDIF FIFO
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[2] FIFO[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[52]

SDIF FIFO
address_offset : 0x8188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[52] FIFO[52] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


PLDMND

Poll Demand register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLDMND PLDMND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD

PD : Poll Demand.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[53]

SDIF FIFO
address_offset : 0x845C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[53] FIFO[53] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[54]

SDIF FIFO
address_offset : 0x8734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[54] FIFO[54] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


DBADDR

Descriptor List Base Address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBADDR DBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDL

SDL : Start of Descriptor List.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[55]

SDIF FIFO
address_offset : 0x8A10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[55] FIFO[55] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


IDSTS

Internal DMAC Status register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDSTS IDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI RI FBE DU CES NIS AIS EB FSM

TI : Transmit Interrupt.
bits : 0 - 0 (1 bit)
access : read-write

RI : Receive Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

FBE : Fatal Bus Error Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

DU : Descriptor Unavailable Interrupt.
bits : 4 - 4 (1 bit)
access : read-write

CES : Card Error Summary.
bits : 5 - 5 (1 bit)
access : read-write

NIS : Normal Interrupt Summary.
bits : 8 - 8 (1 bit)
access : read-write

AIS : Abnormal Interrupt Summary.
bits : 9 - 9 (1 bit)
access : read-write

EB : Error Bits.
bits : 10 - 12 (3 bit)
access : read-write

FSM : DMAC state machine present state.
bits : 13 - 16 (4 bit)
access : read-write


FIFO[56]

SDIF FIFO
address_offset : 0x8CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[56] FIFO[56] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[57]

SDIF FIFO
address_offset : 0x8FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[57] FIFO[57] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


IDINTEN

Internal DMAC Interrupt Enable register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDINTEN IDINTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI RI FBE DU CES NIS AIS

TI : Transmit Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write

RI : Receive Interrupt Enable.
bits : 1 - 1 (1 bit)
access : read-write

FBE : Fatal Bus Error Enable.
bits : 2 - 2 (1 bit)
access : read-write

DU : Descriptor Unavailable Interrupt.
bits : 4 - 4 (1 bit)
access : read-write

CES : Card Error summary Interrupt Enable.
bits : 5 - 5 (1 bit)
access : read-write

NIS : Normal Interrupt Summary Enable.
bits : 8 - 8 (1 bit)
access : read-write

AIS : Abnormal Interrupt Summary Enable.
bits : 9 - 9 (1 bit)
access : read-write


FIFO[58]

SDIF FIFO
address_offset : 0x92BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[58] FIFO[58] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RESP[1]

Response register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[1] RESP[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE

RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write


DSCADDR

Current Host Descriptor Address register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSCADDR DSCADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDA

HDA : Host Descriptor Address Pointer.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[59]

SDIF FIFO
address_offset : 0x95A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[59] FIFO[59] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


BUFADDR

Current Buffer Descriptor Address register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFADDR BUFADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBA

HBA : Host Buffer Address Pointer.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[60]

SDIF FIFO
address_offset : 0x9898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[60] FIFO[60] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[61]

SDIF FIFO
address_offset : 0x9B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[61] FIFO[61] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[62]

SDIF FIFO
address_offset : 0x9E84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[62] FIFO[62] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[3]

SDIF FIFO
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[3] FIFO[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[63]

SDIF FIFO
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[63] FIFO[63] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[4]

SDIF FIFO
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[4] FIFO[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write


RESP[2]

Response register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[2] RESP[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE

RESPONSE : Bits of response.
bits : 0 - 31 (32 bit)
access : read-write


FIFO[5]

SDIF FIFO
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO[5] FIFO[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : SDIF FIFO.
bits : 0 - 31 (32 bit)
access : read-write



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