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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE04 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISER[0]

ICER[0]

IPR[71]

IABR[6]

ISPR[13]

IPR[72]

ISER[11]

IPR[73]

IPR[74]

ICPR[9]

IPR[75]

IPR[76]

ISPR[14]

ITNS[5]

IPR[77]

IPR[78]

IPR[4]

IPR[79]

IABR[7]

IPR[80]

IPR[81]

ICPR[10]

ISPR[15]

IPR[82]

IPR[83]

ISER[12]

IPR[84]

IPR[85]

IPR[86]

ITNS[6]

IPR[87]

ICPR[11]

IABR[8]

IPR[88]

IPR[89]

IPR[5]

IPR[90]

IPR[91]

IPR[92]

IPR[93]

ICPR[12]

IPR[94]

IPR[95]

IABR[9]

ISER[13]

IPR[96]

ITNS[7]

IPR[97]

IPR[98]

IPR[99]

ICPR[13]

ISER[3]

IPR[100]

ICER[1]

IPR[6]

IPR[101]

IPR[102]

IABR[10]

IPR[103]

IPR[104]

IPR[105]

ITNS[8]

ICPR[14]

IPR[106]

IPR[107]

ISER[14]

IPR[108]

IPR[109]

IPR[110]

IABR[11]

IPR[111]

ICPR[15]

IPR[7]

IPR[112]

IPR[113]

IPR[114]

ITNS[9]

IPR[115]

IPR[116]

IPR[117]

IABR[12]

IPR[118]

IPR[119]

ISER[15]

IPR[8]

ITNS[10]

IABR[13]

ISPR[0]

ICER[2]

ITNS[11]

IABR[14]

IPR[9]

IABR[15]

ITNS[12]

IPR[10]

ITNS[13]

ISER[4]

IPR[11]

ICER[3]

ITNS[14]

IPR[12]

ITNS[15]

IPR[13]

ICPR[0]

ISPR[1]

IPR[14]

ICER[4]

IPR[15]

IPR[16]

IPR[17]

ICER[5]

ISER[5]

IPR[18]

ISER[1]

IABR[0]

ISPR[2]

IPR[19]

ICER[6]

IPR[20]

ICPR[1]

IPR[21]

IPR[22]

ICER[7]

IPR[23]

ITNS[0]

ISPR[3]

IPR[24]

ISER[6]

IPR[25]

ICER[8]

IPR[26]

IPR[27]

IPR[0]

IABR[1]

IPR[28]

ICPR[2]

ISPR[4]

ICER[9]

IPR[29]

IPR[30]

IPR[31]

ICER[10]

IPR[32]

ISER[7]

IPR[33]

ISPR[5]

IPR[34]

ITNS[1]

ICER[11]

IPR[35]

ICPR[3]

IPR[36]

IPR[37]

IABR[2]

ICER[12]

IPR[38]

ISPR[6]

IPR[39]

IPR[40]

IPR[41]

ICER[13]

ISER[8]

IPR[1]

IPR[42]

ICPR[4]

IPR[43]

ISPR[7]

IPR[44]

ICER[14]

IPR[45]

ITNS[2]

IPR[46]

IABR[3]

IPR[47]

ICER[15]

IPR[48]

ISPR[8]

ICPR[5]

IPR[49]

IPR[50]

IPR[51]

ISER[9]

IPR[52]

ISPR[9]

IPR[53]

IPR[54]

ISER[2]

IPR[2]

IABR[4]

IPR[55]

ICPR[6]

IPR[56]

ITNS[3]

IPR[57]

ISPR[10]

IPR[58]

IPR[59]

IPR[60]

IPR[61]

ISER[10]

IPR[62]

ICPR[7]

STIR

ISPR[11]

IPR[63]

IABR[5]

IPR[64]

IPR[65]

IPR[66]

IPR[3]

ITNS[4]

IPR[67]

ISPR[12]

IPR[68]

ICPR[8]

IPR[69]

IPR[70]


ISER[0]

Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[0] ISER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


ICER[0]

Interrupt Clear Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[0] ICER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[71]

Interrupt Priority Register
address_offset : 0x102F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[71] IPR[71] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[6]

Interrupt Active Bit Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[6] IABR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ISPR[13]

Interrupt Set Pending Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[13] ISPR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[72]

Interrupt Priority Register
address_offset : 0x10710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[72] IPR[72] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[11]

Interrupt Set Enable Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[11] ISER[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[73]

Interrupt Priority Register
address_offset : 0x10B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[73] IPR[73] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[74]

Interrupt Priority Register
address_offset : 0x10F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[74] IPR[74] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[9]

Interrupt Clear Pending Register
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[9] ICPR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[75]

Interrupt Priority Register
address_offset : 0x11388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[75] IPR[75] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[76]

Interrupt Priority Register
address_offset : 0x117B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[76] IPR[76] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[14]

Interrupt Set Pending Register
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[14] ISPR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


ITNS[5]

Interrupt Target Non-secure Register
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[5] ITNS[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[77]

Interrupt Priority Register
address_offset : 0x11BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[77] IPR[77] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[78]

Interrupt Priority Register
address_offset : 0x12024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[78] IPR[78] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[4]

Interrupt Priority Register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[4] IPR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[79]

Interrupt Priority Register
address_offset : 0x12460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[79] IPR[79] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[7]

Interrupt Active Bit Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[7] IABR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[80]

Interrupt Priority Register
address_offset : 0x128A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[80] IPR[80] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[81]

Interrupt Priority Register
address_offset : 0x12CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[81] IPR[81] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[10]

Interrupt Clear Pending Register
address_offset : 0x12DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[10] ICPR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


ISPR[15]

Interrupt Set Pending Register
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[15] ISPR[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[82]

Interrupt Priority Register
address_offset : 0x1312C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[82] IPR[82] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[83]

Interrupt Priority Register
address_offset : 0x13578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[83] IPR[83] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[12]

Interrupt Set Enable Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[12] ISER[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[84]

Interrupt Priority Register
address_offset : 0x139C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[84] IPR[84] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[85]

Interrupt Priority Register
address_offset : 0x13E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[85] IPR[85] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[86]

Interrupt Priority Register
address_offset : 0x14274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[86] IPR[86] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[6]

Interrupt Target Non-secure Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[6] ITNS[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[87]

Interrupt Priority Register
address_offset : 0x146D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[87] IPR[87] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[11]

Interrupt Clear Pending Register
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[11] ICPR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IABR[8]

Interrupt Active Bit Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[8] IABR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[88]

Interrupt Priority Register
address_offset : 0x14B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[88] IPR[88] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[89]

Interrupt Priority Register
address_offset : 0x14F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[89] IPR[89] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[5]

Interrupt Priority Register
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[5] IPR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[90]

Interrupt Priority Register
address_offset : 0x153FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[90] IPR[90] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[91]

Interrupt Priority Register
address_offset : 0x15868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[91] IPR[91] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[92]

Interrupt Priority Register
address_offset : 0x15CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[92] IPR[92] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[93]

Interrupt Priority Register
address_offset : 0x1614C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[93] IPR[93] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[12]

Interrupt Clear Pending Register
address_offset : 0x1638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[12] ICPR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[94]

Interrupt Priority Register
address_offset : 0x165C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[94] IPR[94] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[95]

Interrupt Priority Register
address_offset : 0x16A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[95] IPR[95] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[9]

Interrupt Active Bit Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[9] IABR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ISER[13]

Interrupt Set Enable Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[13] ISER[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[96]

Interrupt Priority Register
address_offset : 0x16EC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[96] IPR[96] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[7]

Interrupt Target Non-secure Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[7] ITNS[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[97]

Interrupt Priority Register
address_offset : 0x17344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[97] IPR[97] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[98]

Interrupt Priority Register
address_offset : 0x177CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[98] IPR[98] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[99]

Interrupt Priority Register
address_offset : 0x17C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[99] IPR[99] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[13]

Interrupt Clear Pending Register
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[13] ICPR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


ISER[3]

Interrupt Set Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[3] ISER[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[100]

Interrupt Priority Register
address_offset : 0x180E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[100] IPR[100] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[1]

Interrupt Clear Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[1] ICER[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[6]

Interrupt Priority Register
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[6] IPR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[101]

Interrupt Priority Register
address_offset : 0x1857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[101] IPR[101] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[102]

Interrupt Priority Register
address_offset : 0x18A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[102] IPR[102] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[10]

Interrupt Active Bit Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[10] IABR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[103]

Interrupt Priority Register
address_offset : 0x18EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[103] IPR[103] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[104]

Interrupt Priority Register
address_offset : 0x19350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[104] IPR[104] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[105]

Interrupt Priority Register
address_offset : 0x197F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[105] IPR[105] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[8]

Interrupt Target Non-secure Register
address_offset : 0x1990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[8] ITNS[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


ICPR[14]

Interrupt Clear Pending Register
address_offset : 0x19A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[14] ICPR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[106]

Interrupt Priority Register
address_offset : 0x19C9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[106] IPR[106] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[107]

Interrupt Priority Register
address_offset : 0x1A148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[107] IPR[107] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[14]

Interrupt Set Enable Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[14] ISER[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[108]

Interrupt Priority Register
address_offset : 0x1A5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[108] IPR[108] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[109]

Interrupt Priority Register
address_offset : 0x1AAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[109] IPR[109] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[110]

Interrupt Priority Register
address_offset : 0x1AF64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[110] IPR[110] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[11]

Interrupt Active Bit Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[11] IABR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[111]

Interrupt Priority Register
address_offset : 0x1B420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[111] IPR[111] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[15]

Interrupt Clear Pending Register
address_offset : 0x1B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[15] ICPR[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[7]

Interrupt Priority Register
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[7] IPR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[112]

Interrupt Priority Register
address_offset : 0x1B8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[112] IPR[112] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[113]

Interrupt Priority Register
address_offset : 0x1BDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[113] IPR[113] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[114]

Interrupt Priority Register
address_offset : 0x1C26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[114] IPR[114] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[9]

Interrupt Target Non-secure Register
address_offset : 0x1C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[9] ITNS[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[115]

Interrupt Priority Register
address_offset : 0x1C738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[115] IPR[115] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[116]

Interrupt Priority Register
address_offset : 0x1CC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[116] IPR[116] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[117]

Interrupt Priority Register
address_offset : 0x1D0DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[117] IPR[117] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[12]

Interrupt Active Bit Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[12] IABR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[118]

Interrupt Priority Register
address_offset : 0x1D5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[118] IPR[118] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[119]

Interrupt Priority Register
address_offset : 0x1DA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[119] IPR[119] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[15]

Interrupt Set Enable Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[15] ISER[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[8]

Interrupt Priority Register
address_offset : 0x1E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[8] IPR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[10]

Interrupt Target Non-secure Register
address_offset : 0x1EDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[10] ITNS[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IABR[13]

Interrupt Active Bit Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[13] IABR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ISPR[0]

Interrupt Set Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[0] ISPR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


ICER[2]

Interrupt Clear Enable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[2] ICER[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


ITNS[11]

Interrupt Target Non-secure Register
address_offset : 0x2188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[11] ITNS[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IABR[14]

Interrupt Active Bit Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[14] IABR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[9]

Interrupt Priority Register
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[9] IPR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[15]

Interrupt Active Bit Register
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[15] IABR[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ITNS[12]

Interrupt Target Non-secure Register
address_offset : 0x2438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[12] ITNS[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[10]

Interrupt Priority Register
address_offset : 0x24DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[10] IPR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[13]

Interrupt Target Non-secure Register
address_offset : 0x26EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[13] ITNS[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


ISER[4]

Interrupt Set Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[4] ISER[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[11]

Interrupt Priority Register
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[11] IPR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[3]

Interrupt Clear Enable Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[3] ICER[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


ITNS[14]

Interrupt Target Non-secure Register
address_offset : 0x29A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[14] ITNS[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[12]

Interrupt Priority Register
address_offset : 0x2B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[12] IPR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[15]

Interrupt Target Non-secure Register
address_offset : 0x2C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[15] ITNS[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[13]

Interrupt Priority Register
address_offset : 0x2E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[13] IPR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[0]

Interrupt Clear Pending Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[0] ICPR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


ISPR[1]

Interrupt Set Pending Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[1] ISPR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[14]

Interrupt Priority Register
address_offset : 0x31A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[14] IPR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[4]

Interrupt Clear Enable Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[4] ICER[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[15]

Interrupt Priority Register
address_offset : 0x34E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[15] IPR[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[16]

Interrupt Priority Register
address_offset : 0x3820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[16] IPR[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[17]

Interrupt Priority Register
address_offset : 0x3B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[17] IPR[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[5]

Interrupt Clear Enable Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[5] ICER[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


ISER[5]

Interrupt Set Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[5] ISER[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[18]

Interrupt Priority Register
address_offset : 0x3EAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[18] IPR[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[1]

Interrupt Set Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[1] ISER[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IABR[0]

Interrupt Active Bit Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[0] IABR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ISPR[2]

Interrupt Set Pending Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[2] ISPR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[19]

Interrupt Priority Register
address_offset : 0x41F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[19] IPR[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[6]

Interrupt Clear Enable Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[6] ICER[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[20]

Interrupt Priority Register
address_offset : 0x4548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[20] IPR[20] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[1]

Interrupt Clear Pending Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[1] ICPR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[21]

Interrupt Priority Register
address_offset : 0x489C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[21] IPR[21] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[22]

Interrupt Priority Register
address_offset : 0x4BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[22] IPR[22] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[7]

Interrupt Clear Enable Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[7] ICER[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[23]

Interrupt Priority Register
address_offset : 0x4F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[23] IPR[23] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[0]

Interrupt Target Non-secure Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[0] ITNS[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


ISPR[3]

Interrupt Set Pending Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[3] ISPR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[24]

Interrupt Priority Register
address_offset : 0x52B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[24] IPR[24] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[6]

Interrupt Set Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[6] ISER[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[25]

Interrupt Priority Register
address_offset : 0x5614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[25] IPR[25] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[8]

Interrupt Clear Enable Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[8] ICER[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[26]

Interrupt Priority Register
address_offset : 0x597C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[26] IPR[26] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[27]

Interrupt Priority Register
address_offset : 0x5CE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[27] IPR[27] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[0]

Interrupt Priority Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[0] IPR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[1]

Interrupt Active Bit Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[1] IABR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[28]

Interrupt Priority Register
address_offset : 0x6058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[28] IPR[28] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[2]

Interrupt Clear Pending Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[2] ICPR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


ISPR[4]

Interrupt Set Pending Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[4] ISPR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


ICER[9]

Interrupt Clear Enable Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[9] ICER[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[29]

Interrupt Priority Register
address_offset : 0x63CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[29] IPR[29] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[30]

Interrupt Priority Register
address_offset : 0x6744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[30] IPR[30] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[31]

Interrupt Priority Register
address_offset : 0x6AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[31] IPR[31] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[10]

Interrupt Clear Enable Register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[10] ICER[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[32]

Interrupt Priority Register
address_offset : 0x6E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[32] IPR[32] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[7]

Interrupt Set Enable Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[7] ISER[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[33]

Interrupt Priority Register
address_offset : 0x71C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[33] IPR[33] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[5]

Interrupt Set Pending Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[5] ISPR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[34]

Interrupt Priority Register
address_offset : 0x754C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[34] IPR[34] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[1]

Interrupt Target Non-secure Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[1] ITNS[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


ICER[11]

Interrupt Clear Enable Register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[11] ICER[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[35]

Interrupt Priority Register
address_offset : 0x78D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[35] IPR[35] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[3]

Interrupt Clear Pending Register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[3] ICPR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[36]

Interrupt Priority Register
address_offset : 0x7C68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[36] IPR[36] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[37]

Interrupt Priority Register
address_offset : 0x7FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[37] IPR[37] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[2]

Interrupt Active Bit Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[2] IABR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


ICER[12]

Interrupt Clear Enable Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[12] ICER[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[38]

Interrupt Priority Register
address_offset : 0x8394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[38] IPR[38] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[6]

Interrupt Set Pending Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[6] ISPR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[39]

Interrupt Priority Register
address_offset : 0x8730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[39] IPR[39] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[40]

Interrupt Priority Register
address_offset : 0x8AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[40] IPR[40] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[41]

Interrupt Priority Register
address_offset : 0x8E74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[41] IPR[41] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[13]

Interrupt Clear Enable Register
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[13] ICER[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


ISER[8]

Interrupt Set Enable Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[8] ISER[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[1]

Interrupt Priority Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[1] IPR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[42]

Interrupt Priority Register
address_offset : 0x921C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[42] IPR[42] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[4]

Interrupt Clear Pending Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[4] ICPR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[43]

Interrupt Priority Register
address_offset : 0x95C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[43] IPR[43] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[7]

Interrupt Set Pending Register
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[7] ISPR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[44]

Interrupt Priority Register
address_offset : 0x9978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[44] IPR[44] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[14]

Interrupt Clear Enable Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[14] ICER[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[45]

Interrupt Priority Register
address_offset : 0x9D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[45] IPR[45] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[2]

Interrupt Target Non-secure Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[2] ITNS[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[46]

Interrupt Priority Register
address_offset : 0xA0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[46] IPR[46] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[3]

Interrupt Active Bit Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[3] IABR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[47]

Interrupt Priority Register
address_offset : 0xA4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[47] IPR[47] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICER[15]

Interrupt Clear Enable Register
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER[15] ICER[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA0 CLRENA1 CLRENA2 CLRENA3 CLRENA4 CLRENA5 CLRENA6 CLRENA7 CLRENA8 CLRENA9 CLRENA10 CLRENA11 CLRENA12 CLRENA13 CLRENA14 CLRENA15 CLRENA16 CLRENA17 CLRENA18 CLRENA19 CLRENA20 CLRENA21 CLRENA22 CLRENA23 CLRENA24 CLRENA25 CLRENA26 CLRENA27 CLRENA28 CLRENA29 CLRENA30 CLRENA31

CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[48]

Interrupt Priority Register
address_offset : 0xA860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[48] IPR[48] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[8]

Interrupt Set Pending Register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[8] ISPR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


ICPR[5]

Interrupt Clear Pending Register
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[5] ICPR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[49]

Interrupt Priority Register
address_offset : 0xAC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[49] IPR[49] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[50]

Interrupt Priority Register
address_offset : 0xAFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[50] IPR[50] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[51]

Interrupt Priority Register
address_offset : 0xB3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[51] IPR[51] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[9]

Interrupt Set Enable Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[9] ISER[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[52]

Interrupt Priority Register
address_offset : 0xB788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[52] IPR[52] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[9]

Interrupt Set Pending Register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[9] ISPR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[53]

Interrupt Priority Register
address_offset : 0xBB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[53] IPR[53] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[54]

Interrupt Priority Register
address_offset : 0xBF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[54] IPR[54] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[2]

Interrupt Set Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[2] ISER[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[2]

Interrupt Priority Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[2] IPR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[4]

Interrupt Active Bit Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[4] IABR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[55]

Interrupt Priority Register
address_offset : 0xC310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[55] IPR[55] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[6]

Interrupt Clear Pending Register
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[6] ICPR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[56]

Interrupt Priority Register
address_offset : 0xC6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[56] IPR[56] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[3]

Interrupt Target Non-secure Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[3] ITNS[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[57]

Interrupt Priority Register
address_offset : 0xCAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[57] IPR[57] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[10]

Interrupt Set Pending Register
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[10] ISPR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[58]

Interrupt Priority Register
address_offset : 0xCEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[58] IPR[58] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[59]

Interrupt Priority Register
address_offset : 0xD2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[59] IPR[59] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[60]

Interrupt Priority Register
address_offset : 0xD698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[60] IPR[60] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[61]

Interrupt Priority Register
address_offset : 0xDA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[61] IPR[61] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISER[10]

Interrupt Set Enable Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER[10] ISER[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA0 SETENA1 SETENA2 SETENA3 SETENA4 SETENA5 SETENA6 SETENA7 SETENA8 SETENA9 SETENA10 SETENA11 SETENA12 SETENA13 SETENA14 SETENA15 SETENA16 SETENA17 SETENA18 SETENA19 SETENA20 SETENA21 SETENA22 SETENA23 SETENA24 SETENA25 SETENA26 SETENA27 SETENA28 SETENA29 SETENA30 SETENA31

SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.

SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Write: No effect; Read: Interrupt 32n+m disabled

0x1 : ENABLED

Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled

End of enumeration elements list.


IPR[62]

Interrupt Priority Register
address_offset : 0xDE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[62] IPR[62] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[7]

Interrupt Clear Pending Register
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[7] ICPR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


STIR

Software Trigger Interrupt Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STIR STIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt ID of the interrupt to trigger, in the range 0-479.
bits : 0 - 8 (9 bit)
access : write-only


ISPR[11]

Interrupt Set Pending Register
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[11] ISPR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[63]

Interrupt Priority Register
address_offset : 0xE280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[63] IPR[63] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IABR[5]

Interrupt Active Bit Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IABR[5] IABR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE0 ACTIVE1 ACTIVE2 ACTIVE3 ACTIVE4 ACTIVE5 ACTIVE6 ACTIVE7 ACTIVE8 ACTIVE9 ACTIVE10 ACTIVE11 ACTIVE12 ACTIVE13 ACTIVE14 ACTIVE15 ACTIVE16 ACTIVE17 ACTIVE18 ACTIVE19 ACTIVE20 ACTIVE21 ACTIVE22 ACTIVE23 ACTIVE24 ACTIVE25 ACTIVE26 ACTIVE27 ACTIVE28 ACTIVE29 ACTIVE30 ACTIVE31

ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.

ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_ACTIVE

The interrupt is not active.

0x1 : ACTIVE

The interrupt is active.

End of enumeration elements list.


IPR[64]

Interrupt Priority Register
address_offset : 0xE680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[64] IPR[64] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[65]

Interrupt Priority Register
address_offset : 0xEA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[65] IPR[65] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[66]

Interrupt Priority Register
address_offset : 0xEE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[66] IPR[66] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[3]

Interrupt Priority Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[3] IPR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ITNS[4]

Interrupt Target Non-secure Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITNS[4] ITNS[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTS0 INTS1 INTS2 INTS3 INTS4 INTS5 INTS6 INTS7 INTS8 INTS9 INTS10 INTS11 INTS12 INTS13 INTS14 INTS15 INTS16 INTS17 INTS18 INTS19 INTS20 INTS21 INTS22 INTS23 INTS24 INTS25 INTS26 INTS27 INTS28 INTS29 INTS30 INTS31

INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.

INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : SECURE_STATE

The interrupt targets Secure state.

0x1 : NON_SECURE_STATE

The interrupt targets Non-secure state.

End of enumeration elements list.


IPR[67]

Interrupt Priority Register
address_offset : 0xF298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[67] IPR[67] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ISPR[12]

Interrupt Set Pending Register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR[12] ISPR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND0 SETPEND1 SETPEND2 SETPEND3 SETPEND4 SETPEND5 SETPEND6 SETPEND7 SETPEND8 SETPEND9 SETPEND10 SETPEND11 SETPEND12 SETPEND13 SETPEND14 SETPEND15 SETPEND16 SETPEND17 SETPEND18 SETPEND19 SETPEND20 SETPEND21 SETPEND22 SETPEND23 SETPEND24 SETPEND25 SETPEND26 SETPEND27 SETPEND28 SETPEND29 SETPEND30 SETPEND31

SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.

SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending

End of enumeration elements list.


IPR[68]

Interrupt Priority Register
address_offset : 0xF6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[68] IPR[68] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


ICPR[8]

Interrupt Clear Pending Register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR[8] ICPR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND0 CLRPEND1 CLRPEND2 CLRPEND3 CLRPEND4 CLRPEND5 CLRPEND6 CLRPEND7 CLRPEND8 CLRPEND9 CLRPEND10 CLRPEND11 CLRPEND12 CLRPEND13 CLRPEND14 CLRPEND15 CLRPEND16 CLRPEND17 CLRPEND18 CLRPEND19 CLRPEND20 CLRPEND21 CLRPEND22 CLRPEND23 CLRPEND24 CLRPEND25 CLRPEND26 CLRPEND27 CLRPEND28 CLRPEND29 CLRPEND30 CLRPEND31

CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.

CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

0 : NOT_PENDING

Write: No effect; Read: Interrupt 32n+m is not pending

0x1 : PENDING

Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending

End of enumeration elements list.


IPR[69]

Interrupt Priority Register
address_offset : 0xFABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[69] IPR[69] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write


IPR[70]

Interrupt Priority Register
address_offset : 0xFED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR[70] IPR[70] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write

PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write

PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write



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