\n
address_offset : 0x0 Bytes (0x0)
size : 0xE04 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Clear Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x102F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x10710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x10B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x10F5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x11388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x117B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0x11A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Target Non-secure Register
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x11BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x12024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x12460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x128A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x12CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x12DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x12E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1312C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x13578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x139C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x13E1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x14274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x146D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Active Bit Register
address_offset : 0x1490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x14B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x14F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x153FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x15868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x15CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1614C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x1638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x165C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x16A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x16B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Set Enable Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x16EC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x17344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x177CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x17C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Set Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x180E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1857C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x18A14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x18DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x18EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x19350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x197F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x1990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Clear Pending Register
address_offset : 0x19A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x19C9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1A148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1A5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1AAAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1AF64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x1B08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1B420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x1B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1B8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1BDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1C26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x1C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1C738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1CC08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1D0DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x1D38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1D5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x1DA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x1E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x1EDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Active Bit Register
address_offset : 0x1F6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Clear Enable Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Target Non-secure Register
address_offset : 0x2188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Active Bit Register
address_offset : 0x21A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x23E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Target Non-secure Register
address_offset : 0x2438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x24DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x26EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Set Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Target Non-secure Register
address_offset : 0x29A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x2B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x2C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x2E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x31A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x34E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x3820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x3B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Set Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x3EAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Active Bit Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x41F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x4548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x489C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x4BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x4F50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x52B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x5614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x597C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x5CE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x6058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Set Pending Register
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Clear Enable Register
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x63CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x6744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x6AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x6E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x71C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x754C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Clear Enable Register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x78D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x7C68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x7FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Clear Enable Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x8394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x8730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x8AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x8E74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Set Enable Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0x921C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x95C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0x970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x9978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0x9D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xA0E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xA4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Enable Register
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA0 : Interrupt clear-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA1 : Interrupt clear-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA2 : Interrupt clear-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA3 : Interrupt clear-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA4 : Interrupt clear-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA5 : Interrupt clear-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA6 : Interrupt clear-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA7 : Interrupt clear-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA8 : Interrupt clear-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA9 : Interrupt clear-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA10 : Interrupt clear-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA11 : Interrupt clear-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA12 : Interrupt clear-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA13 : Interrupt clear-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA14 : Interrupt clear-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA15 : Interrupt clear-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA16 : Interrupt clear-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA17 : Interrupt clear-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA18 : Interrupt clear-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA19 : Interrupt clear-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA20 : Interrupt clear-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA21 : Interrupt clear-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA22 : Interrupt clear-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA23 : Interrupt clear-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA24 : Interrupt clear-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA25 : Interrupt clear-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA26 : Interrupt clear-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA27 : Interrupt clear-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA28 : Interrupt clear-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA29 : Interrupt clear-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA30 : Interrupt clear-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
CLRENA31 : Interrupt clear-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xA860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Clear Pending Register
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xAC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xAFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xB3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xB788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xBB5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xBF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xC310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xC6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xCAD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0xCDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xCEBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xD2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xD698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xDA8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Enable Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA0 : Interrupt set-enable bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA1 : Interrupt set-enable bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA2 : Interrupt set-enable bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA3 : Interrupt set-enable bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA4 : Interrupt set-enable bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA5 : Interrupt set-enable bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA6 : Interrupt set-enable bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA7 : Interrupt set-enable bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA8 : Interrupt set-enable bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA9 : Interrupt set-enable bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA10 : Interrupt set-enable bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA11 : Interrupt set-enable bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA12 : Interrupt set-enable bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA13 : Interrupt set-enable bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA14 : Interrupt set-enable bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA15 : Interrupt set-enable bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA16 : Interrupt set-enable bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA17 : Interrupt set-enable bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA18 : Interrupt set-enable bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA19 : Interrupt set-enable bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA20 : Interrupt set-enable bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA21 : Interrupt set-enable bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA22 : Interrupt set-enable bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA23 : Interrupt set-enable bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA24 : Interrupt set-enable bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA25 : Interrupt set-enable bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA26 : Interrupt set-enable bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA27 : Interrupt set-enable bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA28 : Interrupt set-enable bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA29 : Interrupt set-enable bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA30 : Interrupt set-enable bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
SETENA31 : Interrupt set-enable bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Write: No effect; Read: Interrupt 32n+m disabled
0x1 : ENABLED
Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xDE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Software Trigger Interrupt Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt ID of the interrupt to trigger, in the range 0-479.
bits : 0 - 8 (9 bit)
access : write-only
Interrupt Set Pending Register
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xE280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Active Bit Register
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE0 : Active state bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE1 : Active state bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE2 : Active state bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE3 : Active state bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE4 : Active state bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE5 : Active state bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE6 : Active state bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE7 : Active state bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE8 : Active state bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE9 : Active state bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE10 : Active state bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE11 : Active state bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE12 : Active state bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE13 : Active state bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE14 : Active state bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE15 : Active state bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE16 : Active state bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE17 : Active state bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE18 : Active state bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE19 : Active state bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE20 : Active state bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE21 : Active state bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE22 : Active state bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE23 : Active state bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE24 : Active state bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE25 : Active state bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE26 : Active state bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE27 : Active state bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE28 : Active state bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE29 : Active state bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE30 : Active state bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
ACTIVE31 : Active state bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_ACTIVE
The interrupt is not active.
0x1 : ACTIVE
The interrupt is active.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xE680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xEA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xEE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Target Non-secure Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Interrupt Targets Non-secure bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS1 : Interrupt Targets Non-secure bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS2 : Interrupt Targets Non-secure bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS3 : Interrupt Targets Non-secure bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS4 : Interrupt Targets Non-secure bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS5 : Interrupt Targets Non-secure bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS6 : Interrupt Targets Non-secure bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS7 : Interrupt Targets Non-secure bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS8 : Interrupt Targets Non-secure bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS9 : Interrupt Targets Non-secure bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS10 : Interrupt Targets Non-secure bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS11 : Interrupt Targets Non-secure bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS12 : Interrupt Targets Non-secure bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS13 : Interrupt Targets Non-secure bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS14 : Interrupt Targets Non-secure bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS15 : Interrupt Targets Non-secure bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS16 : Interrupt Targets Non-secure bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS17 : Interrupt Targets Non-secure bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS18 : Interrupt Targets Non-secure bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS19 : Interrupt Targets Non-secure bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS20 : Interrupt Targets Non-secure bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS21 : Interrupt Targets Non-secure bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS22 : Interrupt Targets Non-secure bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS23 : Interrupt Targets Non-secure bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS24 : Interrupt Targets Non-secure bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS25 : Interrupt Targets Non-secure bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS26 : Interrupt Targets Non-secure bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS27 : Interrupt Targets Non-secure bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS28 : Interrupt Targets Non-secure bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS29 : Interrupt Targets Non-secure bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS30 : Interrupt Targets Non-secure bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
INTS31 : Interrupt Targets Non-secure bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : SECURE_STATE
The interrupt targets Secure state.
0x1 : NON_SECURE_STATE
The interrupt targets Non-secure state.
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xF298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Set Pending Register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND0 : Interrupt set-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND1 : Interrupt set-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND2 : Interrupt set-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND3 : Interrupt set-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND4 : Interrupt set-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND5 : Interrupt set-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND6 : Interrupt set-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND7 : Interrupt set-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND8 : Interrupt set-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND9 : Interrupt set-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND10 : Interrupt set-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND11 : Interrupt set-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND12 : Interrupt set-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND13 : Interrupt set-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND14 : Interrupt set-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND15 : Interrupt set-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND16 : Interrupt set-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND17 : Interrupt set-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND18 : Interrupt set-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND19 : Interrupt set-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND20 : Interrupt set-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND21 : Interrupt set-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND22 : Interrupt set-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND23 : Interrupt set-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND24 : Interrupt set-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND25 : Interrupt set-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND26 : Interrupt set-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND27 : Interrupt set-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND28 : Interrupt set-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND29 : Interrupt set-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND30 : Interrupt set-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
SETPEND31 : Interrupt set-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xF6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Clear Pending Register
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND0 : Interrupt clear-pending bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND1 : Interrupt clear-pending bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND2 : Interrupt clear-pending bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND3 : Interrupt clear-pending bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND4 : Interrupt clear-pending bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND5 : Interrupt clear-pending bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND6 : Interrupt clear-pending bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND7 : Interrupt clear-pending bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND8 : Interrupt clear-pending bits.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND9 : Interrupt clear-pending bits.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND10 : Interrupt clear-pending bits.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND11 : Interrupt clear-pending bits.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND12 : Interrupt clear-pending bits.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND13 : Interrupt clear-pending bits.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND14 : Interrupt clear-pending bits.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND15 : Interrupt clear-pending bits.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND16 : Interrupt clear-pending bits.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND17 : Interrupt clear-pending bits.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND18 : Interrupt clear-pending bits.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND19 : Interrupt clear-pending bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND20 : Interrupt clear-pending bits.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND21 : Interrupt clear-pending bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND22 : Interrupt clear-pending bits.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND23 : Interrupt clear-pending bits.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND24 : Interrupt clear-pending bits.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND25 : Interrupt clear-pending bits.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND26 : Interrupt clear-pending bits.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND27 : Interrupt clear-pending bits.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND28 : Interrupt clear-pending bits.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND29 : Interrupt clear-pending bits.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND30 : Interrupt clear-pending bits.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
CLRPEND31 : Interrupt clear-pending bits.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NOT_PENDING
Write: No effect; Read: Interrupt 32n+m is not pending
0x1 : PENDING
Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending
End of enumeration elements list.
Interrupt Priority Register
address_offset : 0xFABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Interrupt Priority Register
address_offset : 0xFED4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : no description available
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : no description available
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : no description available
bits : 24 - 31 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.