\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SEC_CTRL_APB_BRIDGE0_MEM_CTRL0
SEC_CTRL_APB_BRIDGE0_MEM_CTRL1
SEC_CTRL_APB_BRIDGE0_MEM_CTRL2
SEC_CTRL_APB_BRIDGE1_MEM_CTRL0
SEC_CTRL_APB_BRIDGE1_MEM_CTRL1
SEC_CTRL_APB_BRIDGE1_MEM_CTRL2
SEC_CTRL_APB_BRIDGE1_MEM_CTRL3
SEC_CTRL_AHB_PORT8_SLAVE0_RULE
SEC_CTRL_AHB_PORT8_SLAVE1_RULE
SEC_CTRL_AHB_PORT9_SLAVE0_RULE
SEC_CTRL_AHB_PORT9_SLAVE1_RULE
SEC_CTRL_AHB_PORT10_SLAVE0_RULE
SEC_CTRL_AHB_PORT10_SLAVE1_RULE
SEC_CTRL_AHB_SEC_CTRL_MEM_RULE
SEC_CTRL_APB_BRIDGE_SLAVE_RULE
Security access rules for Flash and ROM slaves.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_RULE : Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
ROM_RULE : Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCON_RULE : System Configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
IOCON_RULE : I/O Configuration
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
GINT0_RULE : GPIO input Interrupt 0
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
GINT1_RULE : GPIO input Interrupt 1
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PINT_RULE : Pin Interrupt and Pattern match
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SEC_PINT_RULE : Secure Pin Interrupt and Pattern match
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
INPUTMUX_RULE : Peripheral input multiplexing
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTIMER0_RULE : Standard counter/Timer 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CTIMER1_RULE : Standard counter/Timer 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
WWDT_RULE : Windiwed wtachdog Timer
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
MRT_RULE : Multi-rate Timer
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
UTICK_RULE : Micro-Timer
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANACTRL_RULE : Analog Modules controller
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMC_RULE : Power Management Controller
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SYSCTRL_RULE : System Controller
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTIMER2_RULE : Standard counter/Timer 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CTIMER3_RULE : Standard counter/Timer 3
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CTIMER4_RULE : Standard counter/Timer 4
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RTC_RULE : Real Time Counter
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
OSEVENT_RULE : OS Event Timer
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_CTRL_RULE : Flash Controller
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PRINCE_RULE : Prince
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBHPHY_RULE : USB High Speed Phy controller
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RNG_RULE : True Random Number Generator
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PUF_RULE : PUF
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PLU_RULE : Programmable Look-Up logic
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_RULE : DMA Controller
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FS_USB_DEV_RULE : USB Full-speed device
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SCT_RULE : SCTimer
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM0_RULE : Flexcomm interface 0
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM1_RULE : Flexcomm interface 1
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXCOMM2_RULE : Flexcomm interface 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM3_RULE : Flexcomm interface 3
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM4_RULE : Flexcomm interface 4
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
MAILBOX_RULE : Inter CPU communication Mailbox
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
GPIO0_RULE : High Speed GPIO
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_HS_DEV_RULE : USB high Speed device registers
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CRC_RULE : CRC engine
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM5_RULE : Flexcomm interface 5
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
FLEXCOMM6_RULE : Flexcomm interface 6
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXCOMM7_RULE : Flexcomm interface 7
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SDIO_RULE : SDMMC card interface
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
DBG_MAILBOX_RULE : Debug mailbox (aka ISP-AP)
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
HS_LSPI_RULE : High Speed SPI
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_RULE : ADC
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
USB_FS_HOST_RULE : USB Full Speed Host registers.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
USB_HS_HOST_RULE : USB High speed host registers
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
HASH_RULE : SHA-2 crypto registers
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CASPER_RULE : RSA/ECC crypto accelerator
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PQ_RULE : Power Quad (CPU0 processor hardware accelerator)
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
DMA1_RULE : DMA Controller (Secure)
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB peripherals.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO1_RULE : Secure High Speed GPIO
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
AHB_SEC_CTRL_RULE : AHB Secure Controller
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for AHB_SEC_CTRL_AHB.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB_SEC_CTRL_SECT_0_RULE : Address space: 0x400A_0000 - 0x400A_CFFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
AHB_SEC_CTRL_SECT_1_RULE : Address space: 0x400A_D000 - 0x400A_DFFF
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
AHB_SEC_CTRL_SECT_2_RULE : Address space: 0x400A_E000 - 0x400A_EFFF
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
AHB_SEC_CTRL_SECT_3_RULE : Address space: 0x400A_F000 - 0x400A_FFFF
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for USB High speed RAM slaves.
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM_USB_HS_RULE : Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for RAM_USB_HS.
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM_SECT_0_RULE : Address space: 0x4010_0000 - 0x4010_0FFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SRAM_SECT_1_RULE : Address space: 0x4010_1000 - 0x4010_1FFF
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SRAM_SECT_2_RULE : Address space: 0x4010_2000 - 0x4010_2FFF
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SRAM_SECT_3_RULE : Address space: 0x4010_3000 - 0x4010_3FFF
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x1C00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x1D00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x2A04 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x2B84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for RAMX slaves.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMX_RULE : Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x380C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x3A0C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAMX slaves.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x4618 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x4898 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM0 slaves.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM0_RULE : Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x5428 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x5728 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM0 slaves.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x623C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
Security access rules for RAM0 slaves.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation miscellaneous information for AHB port n
address_offset : 0x65BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM1 slaves.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM1_RULE : Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x7054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0x7454 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x7E70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
Security access rules for RAM1 slaves.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation miscellaneous information for AHB port n
address_offset : 0x82F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM1 slaves.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x8C90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
Security access rules for RAM2 slaves.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM2_RULE : Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation miscellaneous information for AHB port n
address_offset : 0x9190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0x9AB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
Security access rules for RAM2 slaves.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation miscellaneous information for AHB port n
address_offset : 0xA034 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM2 slaves.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0xA8DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0xAEDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM3 slaves.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM3_RULE : Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
most recent security violation address for AHB port n
address_offset : 0xB708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_ADDR : security violation address for AHB port
bits : 0 - 31 (32 bit)
access : read-only
most recent security violation miscellaneous information for AHB port n
address_offset : 0xBD88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_VIO_INFO_WRITE : security violation access read/write indicator.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : READ
Read access.
0x1 : WRITE
Write access.
End of enumeration elements list.
SEC_VIO_INFO_DATA_ACCESS : security violation access data/code indicator.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : CODE
Code access.
0x1 : DATA
Data access.
End of enumeration elements list.
SEC_VIO_INFO_MASTER_SEC_LEVEL : bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
bits : 4 - 7 (4 bit)
access : read-only
SEC_VIO_INFO_MASTER : security violation master number
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : VALUE_0
CPU0 Code.
0x1 : VALUE_1
CPU0 System.
0x2 : VALUE_2
CPU1 Data.
0x3 : VALUE_3
CPU1 System.
0x4 : VALUE_4
USB-HS Device.
0x5 : VALUE_5
SDMA0.
0x8 : VALUE_8
SDIO.
0x9 : VALUE_9
PowerQuad.
0xA : VALUE_10
HASH.
0xB : VALUE_11
USB-FS Host.
0xC : VALUE_12
SDMA1.
End of enumeration elements list.
Security access rules for RAM3 slaves.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for RAM3 slaves.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE4 : secure control rule4. it can be set when check_reg's write_lock is '0'
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE5 : secure control rule5. it can be set when check_reg's write_lock is '0'
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE6 : secure control rule6. it can be set when check_reg's write_lock is '0'
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE7 : secure control rule7. it can be set when check_reg's write_lock is '0'
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for RAM4 slaves.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM4_RULE : Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for RAM4 slaves.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RULE0 : secure control rule0. it can be set when check_reg's write_lock is '0'
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE1 : secure control rule1. it can be set when check_reg's write_lock is '0'
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE2 : secure control rule2. it can be set when check_reg's write_lock is '0'
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
RULE3 : secure control rule3. it can be set when check_reg's write_lock is '0'
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
Security access rules for both APB Bridges slaves.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APBBRIDGE0_RULE : Security access rules for the whole APB Bridge 0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
APBBRIDGE1_RULE : Security access rules for the whole APB Bridge 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
security violation address/information registers valid flags
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIO_INFO_VALID0 : violation information valid flag for AHB port 0. Write 1 to clear.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID1 : violation information valid flag for AHB port 1. Write 1 to clear.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID2 : violation information valid flag for AHB port 2. Write 1 to clear.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID3 : violation information valid flag for AHB port 3. Write 1 to clear.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID4 : violation information valid flag for AHB port 4. Write 1 to clear.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID5 : violation information valid flag for AHB port 5. Write 1 to clear.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID6 : violation information valid flag for AHB port 6. Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID7 : violation information valid flag for AHB port 7. Write 1 to clear.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID8 : violation information valid flag for AHB port 8. Write 1 to clear.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID9 : violation information valid flag for AHB port 9. Write 1 to clear.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID10 : violation information valid flag for AHB port 10. Write 1 to clear.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
VIO_INFO_VALID11 : violation information valid flag for AHB port 11. Write 1 to clear.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : NOT_VALID
Not valid.
0x1 : VALID
Valid (violation occurred).
End of enumeration elements list.
Secure GPIO mask for port 0 pins.
address_offset : 0xF80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIO0_PIN0_SEC_MASK : Secure mask for pin P0_0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN1_SEC_MASK : Secure mask for pin P0_1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN2_SEC_MASK : Secure mask for pin P0_2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN3_SEC_MASK : Secure mask for pin P0_3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN4_SEC_MASK : Secure mask for pin P0_4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN5_SEC_MASK : Secure mask for pin P0_5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN6_SEC_MASK : Secure mask for pin P0_6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN7_SEC_MASK : Secure mask for pin P0_7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN8_SEC_MASK : Secure mask for pin P0_8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN9_SEC_MASK : Secure mask for pin P0_9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN10_SEC_MASK : Secure mask for pin P0_10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN11_SEC_MASK : Secure mask for pin P0_11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN12_SEC_MASK : Secure mask for pin P0_12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN13_SEC_MASK : Secure mask for pin P0_13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN14_SEC_MASK : Secure mask for pin P0_14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN15_SEC_MASK : Secure mask for pin P0_15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN16_SEC_MASK : Secure mask for pin P0_16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN17_SEC_MASK : Secure mask for pin P0_17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN18_SEC_MASK : Secure mask for pin P0_18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN19_SEC_MASK : Secure mask for pin P0_19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN20_SEC_MASK : Secure mask for pin P0_20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN21_SEC_MASK : Secure mask for pin P0_21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN22_SEC_MASK : Secure mask for pin P0_22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN23_SEC_MASK : Secure mask for pin P0_23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN24_SEC_MASK : Secure mask for pin P0_24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN25_SEC_MASK : Secure mask for pin P0_25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN26_SEC_MASK : Secure mask for pin P0_26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN27_SEC_MASK : Secure mask for pin P0_27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN28_SEC_MASK : Secure mask for pin P0_28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN29_SEC_MASK : Secure mask for pin P0_29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN30_SEC_MASK : Secure mask for pin P0_30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO0_PIN31_SEC_MASK : Secure mask for pin P0_31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
Secure GPIO mask for port 1 pins.
address_offset : 0xF84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIO1_PIN0_SEC_MASK : Secure mask for pin P1_0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN1_SEC_MASK : Secure mask for pin P1_1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN2_SEC_MASK : Secure mask for pin P1_2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN3_SEC_MASK : Secure mask for pin P1_3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN4_SEC_MASK : Secure mask for pin P1_4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN5_SEC_MASK : Secure mask for pin P1_5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN6_SEC_MASK : Secure mask for pin P1_6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN7_SEC_MASK : Secure mask for pin P1_7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN8_SEC_MASK : Secure mask for pin P1_8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN9_SEC_MASK : Secure mask for pin P1_9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN10_SEC_MASK : Secure mask for pin P1_10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN11_SEC_MASK : Secure mask for pin P1_11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN12_SEC_MASK : Secure mask for pin P1_12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN13_SEC_MASK : Secure mask for pin P1_13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN14_SEC_MASK : Secure mask for pin P1_14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN15_SEC_MASK : Secure mask for pin P1_15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN16_SEC_MASK : Secure mask for pin P1_16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN17_SEC_MASK : Secure mask for pin P1_17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN18_SEC_MASK : Secure mask for pin P1_18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN19_SEC_MASK : Secure mask for pin P1_19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN20_SEC_MASK : Secure mask for pin P1_20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN21_SEC_MASK : Secure mask for pin P1_21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN22_SEC_MASK : Secure mask for pin P1_22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN23_SEC_MASK : Secure mask for pin P1_23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN24_SEC_MASK : Secure mask for pin P1_24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN25_SEC_MASK : Secure mask for pin P1_25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN26_SEC_MASK : Secure mask for pin P1_26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN27_SEC_MASK : Secure mask for pin P1_27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN28_SEC_MASK : Secure mask for pin P1_28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN29_SEC_MASK : Secure mask for pin P1_29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN30_SEC_MASK : Secure mask for pin P1_30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
PIO1_PIN31_SEC_MASK : Secure mask for pin P1_31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : BLOCKED
Pin state is blocked to non-secure world.
0x1 : READABLE
Pin state is readable by non-secure world.
End of enumeration elements list.
Secure Interrupt mask for CPU1
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_IRQ : Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SDMA0_IRQ : System DMA 0 (non-secure) interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_GLOBALINT0_IRQ : GPIO Group 0 interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_GLOBALINT1_IRQ : GPIO Group 1 interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ0 : Pin interrupt 0 or pattern match engine slice 0 interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ1 : Pin interrupt 1 or pattern match engine slice 1 interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ2 : Pin interrupt 2 or pattern match engine slice 2 interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ3 : Pin interrupt 3 or pattern match engine slice 3 interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
UTICK_IRQ : Micro Tick Timer interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
MRT_IRQ : Multi-Rate Timer interrupt.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CTIMER0_IRQ : Standard counter/timer 0 interrupt.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CTIMER1_IRQ : Standard counter/timer 1 interrupt.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SCT_IRQ : SCTimer/PWM interrupt.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CTIMER3_IRQ : Standard counter/timer 3 interrupt.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM0_IRQ : Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM1_IRQ : Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM2_IRQ : Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM3_IRQ : Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM4_IRQ : Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM5_IRQ : Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM6_IRQ : Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
FLEXCOMM7_IRQ : Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
ADC_IRQ : General Purpose ADC interrupt.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED0 : Reserved. Read value is undefined, only zero should be written.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
ACMP_IRQ : Analog Comparator interrupt.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED1 : Reserved. Read value is undefined, only zero should be written.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED2 : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
USB0_NEEDCLK : USB Full Speed Controller Clock request interrupt.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
USB0_IRQ : USB Full Speed Controller interrupt.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RTC_IRQ : RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED3 : Reserved. Read value is undefined, only zero should be written.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
MAILBOX_IRQ : Mailbox interrupt.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
Secure Interrupt mask for CPU1
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_INT0_IRQ4 : Pin interrupt 4 or pattern match engine slice 4 interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ5 : Pin interrupt 5 or pattern match engine slice 5 interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ6 : Pin interrupt 6 or pattern match engine slice 6 interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
GPIO_INT0_IRQ7 : Pin interrupt 7 or pattern match engine slice 7 interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CTIMER2_IRQ : Standard counter/timer 2 interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CTIMER4_IRQ : Standard counter/timer 4 interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
OS_EVENT_TIMER_IRQ : OS Event Timer and OS Event Timer Wakeup interrupts
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED0 : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED1 : Reserved. Read value is undefined, only zero should be written.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED2 : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SDIO_IRQ : SDIO Controller interrupt.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED3 : Reserved. Read value is undefined, only zero should be written.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED4 : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
RESERVED5 : Reserved. Read value is undefined, only zero should be written.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
USB1_PHY_IRQ : USB High Speed PHY Controller interrupt.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
USB1_IRQ : USB High Speed Controller interrupt.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
USB1_NEEDCLK : USB High Speed Controller Clock request interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SEC_HYPERVISOR_CALL_IRQ : Secure fault Hyper Visor call interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SEC_GPIO_INT0_IRQ0 : Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SEC_GPIO_INT0_IRQ1 : Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
PLU_IRQ : Programmable Look-Up Controller interrupt.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SEC_VIO_IRQ : Security Violation interrupt.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SHA_IRQ : HASH-AES interrupt.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
CASPER_IRQ : CASPER interrupt.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
PUFKEY_IRQ : PUF interrupt.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
PQ_IRQ : Power Quad interrupt.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
SDMA1_IRQ : System DMA 1 (Secure) interrupt
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
LSPI_HS_IRQ : High Speed SPI interrupt
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : INVISIBLE
no description available
0x1 : VISIBLE
no description available
End of enumeration elements list.
Security General Purpose register access control.
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC_GPIO_MASK0_LOCK : SEC_GPIO_MASK0 register write-lock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
SEC_GPIO_MASK1_LOCK : SEC_GPIO_MASK1 register write-lock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
SEC_CPU1_INT_MASK0_LOCK : SEC_CPU_INT_MASK0 register write-lock.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
SEC_CPU1_INT_MASK1_LOCK : SEC_CPU_INT_MASK1 register write-lock.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
master secure level register
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1C : Micro-Cortex M33 (CPU1) Code bus.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
CPU1S : Micro-Cortex M33 (CPU1) System bus.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
USBFSD : USB Full Speed Device.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SDMA0 : System DMA 0.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SDIO : SDIO.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
PQ : Power Quad.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
HASH : Hash.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
USBFSH : USB Full speed Host.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
SDMA1 : System DMA 1 security level.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
0x1 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x2 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x3 : ENUM_S_P
Secure and Priviledge user access allowed.
End of enumeration elements list.
MASTER_SEC_LEVEL_LOCK : MASTER_SEC_LEVEL write-lock.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
master secure level anti-pole register
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPU1C : Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
CPU1S : Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
USBFSD : USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
SDMA0 : System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
SDIO : SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
PQ : Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
HASH : Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
USBFSH : USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
SDMA1 : System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : ENUM_S_P
Secure and Priviledge user access allowed.
0x1 : ENUM_S_NP
Secure and Non-priviledge user access allowed.
0x2 : ENUM_NS_P
Non-secure and Privilege access allowed.
0x3 : ENUM_NS_NP
Non-secure and Non-priviledge user access allowed.
End of enumeration elements list.
MASTER_SEC_LEVEL_ANTIPOL_LOCK : MASTER_SEC_ANTI_POL_REG register write-lock.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
Miscalleneous control signals for in Cortex M33 (CPU0)
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_NS_VTOR : Cortex M33 (CPU0) VTOR_NS register write-lock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
LOCK_NS_MPU : Cortex M33 (CPU0) non-secure MPU register write-lock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
LOCK_S_VTAIRCR : Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
LOCK_S_MPU : Cortex M33 (CPU0) Secure MPU registers write-lock.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
LOCK_SAU : Cortex M33 (CPU0) SAU registers write-lock.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
CPU0_LOCK_REG_LOCK : CPU0_LOCK_REG write-lock.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
Miscalleneous control signals for in micro-Cortex M33 (CPU1)
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK_NS_VTOR : micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
LOCK_NS_MPU : micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
CPU1_LOCK_REG_LOCK : CPU1_LOCK_REG write-lock.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x1 : BLOCKED
Restricted mode.
0x2 : WRITABLE
Writable.
End of enumeration elements list.
secure control duplicate register
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRITE_LOCK : Write lock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : RESTRICTED
Restricted mode.
0x2 : ACCESSIBLE
Secure control registers can be written.
End of enumeration elements list.
ENABLE_SECURE_CHECKING : Enable secure check for AHB matrix.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
ENABLE_S_PRIV_CHECK : Enable secure privilege check for AHB matrix.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
ENABLE_NS_PRIV_CHECK : Enable non-secure privilege check for AHB matrix.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
DISABLE_VIOLATION_ABORT : Disable secure violation abort.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Disable abort fort secure checker.
0x2 : ENABLE
Enable abort fort secure checker.
End of enumeration elements list.
DISABLE_SIMPLE_MASTER_STRICT_MODE : Disable simple master strict mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x1 : TIER_MODE
Simple master in tier mode.
0x2 : STRICT_MODE
Simple master in strict mode.
End of enumeration elements list.
DISABLE_SMART_MASTER_STRICT_MODE : Disable smart master strict mode.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x1 : TIER_MODE
Smart master in tier mode.
0x2 : STRICT_MODE
Smart master in strict mode.
End of enumeration elements list.
IDAU_ALL_NS : Disable IDAU.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
IDAU is disable.
0x2 : ENABLE
IDAU is enabled.
End of enumeration elements list.
secure control register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRITE_LOCK : Write lock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x1 : RESTRICTED
Restricted mode.
0x2 : ACCESSIBLE
Secure control registers can be written.
End of enumeration elements list.
ENABLE_SECURE_CHECKING : Enable secure check for AHB matrix.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
ENABLE_S_PRIV_CHECK : Enable secure privilege check for AHB matrix.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
ENABLE_NS_PRIV_CHECK : Enable non-secure privilege check for AHB matrix.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0x1 : ENABLE
Restricted mode.
0x2 : DISABLE
Disable check.
End of enumeration elements list.
DISABLE_VIOLATION_ABORT : Disable secure violation abort.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
Disable abort fort secure checker.
0x2 : ENABLE
Enable abort fort secure checker.
End of enumeration elements list.
DISABLE_SIMPLE_MASTER_STRICT_MODE : Disable simple master strict mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x1 : TIER_MODE
Simple master in tier mode.
0x2 : STRICT_MODE
Simple master in strict mode.
End of enumeration elements list.
DISABLE_SMART_MASTER_STRICT_MODE : Disable smart master strict mode.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x1 : TIER_MODE
Smart master in tier mode.
0x2 : STRICT_MODE
Smart master in strict mode.
End of enumeration elements list.
IDAU_ALL_NS : Disable IDAU.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x1 : DISABLE
IDAU is disable.
0x2 : ENABLE
IDAU is enabled.
End of enumeration elements list.
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