Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection : not protected
Configuration for shared functions.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTEN : Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The I2C Master function is disabled.
0x1 : ENABLED
Enabled. The I2C Master function is enabled.
End of enumeration elements list.
SLVEN : Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The I2C slave function is disabled.
0x1 : ENABLED
Enabled. The I2C slave function is enabled.
End of enumeration elements list.
MONEN : Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The I2C Monitor function is disabled.
0x1 : ENABLED
Enabled. The I2C Monitor function is enabled.
End of enumeration elements list.
TIMEOUTEN : I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. Time-out function is disabled.
0x1 : ENABLED
Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
End of enumeration elements list.
MONCLKSTR : Monitor function Clock Stretching.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0x1 : ENABLED
Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
End of enumeration elements list.
Time-out value register.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOMIN : Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
bits : 0 - 3 (4 bit)
access : read-write
TO : Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
bits : 4 - 15 (12 bit)
access : read-write
Slave address register.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVVAL : This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status register for Master, Slave, and Monitor functions.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MSTPENDING : Master Pending.
bits : 0 - 0 (1 bit)
access : read-only
MSTARBLOSS : Master Arbitration Loss flag.
bits : 4 - 4 (1 bit)
access : read-only
MSTSTSTPERR : Master Start/Stop Error flag.
bits : 6 - 6 (1 bit)
access : read-only
SLVPENDING : Slave Pending.
bits : 8 - 8 (1 bit)
access : read-only
SLVNOTSTR : Slave Not Stretching status.
bits : 11 - 11 (1 bit)
access : read-only
SLVDESEL : Slave Deselected flag.
bits : 15 - 15 (1 bit)
access : read-only
MONRDY : Monitor Ready.
bits : 16 - 16 (1 bit)
access : read-only
MONOV : Monitor Overflow flag.
bits : 17 - 17 (1 bit)
access : read-only
MONIDLE : Monitor Idle flag.
bits : 19 - 19 (1 bit)
access : read-only
EVENTTIMEOUT : Event time-out Interrupt flag.
bits : 24 - 24 (1 bit)
access : read-only
SCLTIMEOUT : SCL time-out Interrupt flag.
bits : 25 - 25 (1 bit)
access : read-only
Slave address register.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Master control register.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTCONTINUE : Master Continue.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect.
0x1 : Continue
Informs the Master function to continue to the next operation.
End of enumeration elements list.
MSTSTART : Master Start control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect.
0x1 : START
Start. A Start will be generated on the I2C bus at the next allowed time.
End of enumeration elements list.
MSTSTOP : Master Stop control.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect.
0x1 : STOP
Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).
End of enumeration elements list.
Master timing configuration.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTSCLLOW : Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU STA have the same values and are also controlled by MSTSCLLOW.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : CLOCKS_2
2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0x1 : CLOCKS_3
3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x2 : CLOCKS_4
4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x3 : CLOCKS_5
5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x4 : CLOCKS_6
6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x5 : CLOCKS_7
7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x6 : CLOCKS_8
8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x7 : CLOCKS_9
9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
End of enumeration elements list.
MSTSCLHIGH : Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU STO and tHD STA have the same values and are also controlled by MSTSCLHIGH.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : CLOCKS_2
2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0x1 : CLOCKS_3
3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x2 : CLOCKS_4
4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x3 : CLOCKS_5
5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x4 : CLOCKS_6
6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x5 : CLOCKS_7
7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x6 : CLOCKS_8
8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x7 : CLOCKS_9
9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
End of enumeration elements list.
Combined Master receiver and transmitter data register.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
bits : 0 - 7 (8 bit)
access : read-write
Status register for Master, Slave, and Monitor functions.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTPENDING : Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : IN_PROGRESS
In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0x1 : PENDING
Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
End of enumeration elements list.
MSTSTATE : Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.
bits : 1 - 3 (3 bit)
access : read-only
Enumeration:
0 : IDLE
Idle. The Master function is available to be used for a new transaction.
0x1 : RECEIVE_READY
Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x2 : TRANSMIT_READY
Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x3 : NACK_ADDRESS
NACK Address. Slave NACKed address.
0x4 : NACK_DATA
NACK Data. Slave NACKed transmitted data.
End of enumeration elements list.
MSTARBLOSS : Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NO_LOSS
No Arbitration Loss has occurred.
0x1 : ARBITRATION_LOSS
Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
End of enumeration elements list.
MSTSTSTPERR : Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NO_ERROR
No Start/Stop Error has occurred.
0x1 : ERROR
The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
End of enumeration elements list.
SLVPENDING : Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : IN_PROGRESS
In progress. The Slave function does not currently need service.
0x1 : PENDING
Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
End of enumeration elements list.
SLVSTATE : Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.
bits : 9 - 10 (2 bit)
access : read-only
Enumeration:
0 : SLAVE_ADDRESS
Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0x1 : SLAVE_RECEIVE
Slave receive. Received data is available (Slave Receiver mode).
0x2 : SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave Transmitter mode).
End of enumeration elements list.
SLVNOTSTR : Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : STRETCHING
Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0x1 : NOT_STRETCHING
Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
End of enumeration elements list.
SLVIDX : Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0 : ADDRESS0
Address 0. Slave address 0 was matched.
0x1 : ADDRESS1
Address 1. Slave address 1 was matched.
0x2 : ADDRESS2
Address 2. Slave address 2 was matched.
0x3 : ADDRESS3
Address 3. Slave address 3 was matched.
End of enumeration elements list.
SLVSEL : Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : NOT_SELECTED
Not selected. The Slave function is not currently selected.
0x1 : SELECTED
Selected. The Slave function is currently selected.
End of enumeration elements list.
SLVDESEL : Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NOT_DESELECTED
Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0x1 : DESELECTED
Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
End of enumeration elements list.
MONRDY : Monitor Ready. This flag is cleared when the MONRXDAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : NO_DATA
No data. The Monitor function does not currently have data available.
0x1 : DATA_WAITING
Data waiting. The Monitor function has data waiting to be read.
End of enumeration elements list.
MONOV : Monitor Overflow flag.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NO_OVERRUN
No overrun. Monitor data has not overrun.
0x1 : OVERRUN
Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
End of enumeration elements list.
MONACTIVE : Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : INACTIVE
Inactive. The Monitor function considers the I2C bus to be inactive.
0x1 : ACTIVE
Active. The Monitor function considers the I2C bus to be active.
End of enumeration elements list.
MONIDLE : Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0x1 : IDLE
Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
End of enumeration elements list.
EVENTTIMEOUT : Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : NO_TIMEOUT
No time-out. I2C bus events have not caused a time-out.
0x1 : EVEN_TIMEOUT
Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
End of enumeration elements list.
SCLTIMEOUT : SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_TIMEOUT
No time-out. SCL low time has not caused a time-out.
0x1 : TIMEOUT
Time-out. SCL low time has caused a time-out.
End of enumeration elements list.
Slave control register.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLVCONTINUE : Slave Continue.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect.
0x1 : Continue
Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
End of enumeration elements list.
SLVNACK : Slave NACK.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect.
0x1 : NACK
NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
End of enumeration elements list.
Combined Slave receiver and transmitter data register.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
bits : 0 - 7 (8 bit)
access : read-write
Slave address register.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Slave address register.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Slave address register.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Slave address register.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Slave Qualification for address 0.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUALMODE0 : Qualify mode for slave address 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : MASK
Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
0x1 : EXTEND
Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
End of enumeration elements list.
SLVQUAL0 : Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
bits : 1 - 7 (7 bit)
access : read-write
Interrupt Enable Set and read register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTPENDINGEN : Master Pending interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MstPending interrupt is disabled.
0x1 : ENABLED
Enabled. The MstPending interrupt is enabled.
End of enumeration elements list.
MSTARBLOSSEN : Master Arbitration Loss interrupt Enable.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MstArbLoss interrupt is disabled.
0x1 : ENABLED
Enabled. The MstArbLoss interrupt is enabled.
End of enumeration elements list.
MSTSTSTPERREN : Master Start/Stop Error interrupt Enable.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MstStStpErr interrupt is disabled.
0x1 : ENABLED
Enabled. The MstStStpErr interrupt is enabled.
End of enumeration elements list.
SLVPENDINGEN : Slave Pending interrupt Enable.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SlvPending interrupt is disabled.
0x1 : ENABLED
Enabled. The SlvPending interrupt is enabled.
End of enumeration elements list.
SLVNOTSTREN : Slave Not Stretching interrupt Enable.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SlvNotStr interrupt is disabled.
0x1 : ENABLED
Enabled. The SlvNotStr interrupt is enabled.
End of enumeration elements list.
SLVDESELEN : Slave Deselect interrupt Enable.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SlvDeSel interrupt is disabled.
0x1 : ENABLED
Enabled. The SlvDeSel interrupt is enabled.
End of enumeration elements list.
MONRDYEN : Monitor data Ready interrupt Enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MonRdy interrupt is disabled.
0x1 : ENABLED
Enabled. The MonRdy interrupt is enabled.
End of enumeration elements list.
MONOVEN : Monitor Overrun interrupt Enable.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MonOv interrupt is disabled.
0x1 : ENABLED
Enabled. The MonOv interrupt is enabled.
End of enumeration elements list.
MONIDLEEN : Monitor Idle interrupt Enable.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The MonIdle interrupt is disabled.
0x1 : ENABLED
Enabled. The MonIdle interrupt is enabled.
End of enumeration elements list.
EVENTTIMEOUTEN : Event time-out interrupt Enable.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The Event time-out interrupt is disabled.
0x1 : ENABLED
Enabled. The Event time-out interrupt is enabled.
End of enumeration elements list.
SCLTIMEOUTEN : SCL time-out interrupt Enable.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SCL time-out interrupt is disabled.
0x1 : ENABLED
Enabled. The SCL time-out interrupt is enabled.
End of enumeration elements list.
Monitor receiver data register.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MONRXDAT : Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
bits : 0 - 7 (8 bit)
access : read-only
MONSTART : Monitor Received Start.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : NO_START_DETECTED
No start detected. The Monitor function has not detected a Start event on the I2C bus.
0x1 : START_DETECTED
Start detected. The Monitor function has detected a Start event on the I2C bus.
End of enumeration elements list.
MONRESTART : Monitor Received Repeated Start.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : NOT_DETECTED
No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0x1 : DETECTED
Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
End of enumeration elements list.
MONNACK : Monitor Received NACK.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : ACKNOWLEDGED
Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0x1 : NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
End of enumeration elements list.
Slave address register.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
Interrupt Enable Clear register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MSTPENDINGCLR : Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
bits : 0 - 0 (1 bit)
access : write-only
MSTARBLOSSCLR : Master Arbitration Loss interrupt clear.
bits : 4 - 4 (1 bit)
access : write-only
MSTSTSTPERRCLR : Master Start/Stop Error interrupt clear.
bits : 6 - 6 (1 bit)
access : write-only
SLVPENDINGCLR : Slave Pending interrupt clear.
bits : 8 - 8 (1 bit)
access : write-only
SLVNOTSTRCLR : Slave Not Stretching interrupt clear.
bits : 11 - 11 (1 bit)
access : write-only
SLVDESELCLR : Slave Deselect interrupt clear.
bits : 15 - 15 (1 bit)
access : write-only
MONRDYCLR : Monitor data Ready interrupt clear.
bits : 16 - 16 (1 bit)
access : write-only
MONOVCLR : Monitor Overrun interrupt clear.
bits : 17 - 17 (1 bit)
access : write-only
MONIDLECLR : Monitor Idle interrupt clear.
bits : 19 - 19 (1 bit)
access : write-only
EVENTTIMEOUTCLR : Event time-out interrupt clear.
bits : 24 - 24 (1 bit)
access : write-only
SCLTIMEOUTCLR : SCL time-out interrupt clear.
bits : 25 - 25 (1 bit)
access : write-only
Slave address register.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADISABLE : Slave Address n Disable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ENABLED
Enabled. Slave Address n is enabled.
0x1 : DISABLED
Ignored Slave Address n is ignored.
End of enumeration elements list.
SLVADR : Slave Address. Seven bit slave address that is compared to received addresses if enabled.
bits : 1 - 7 (7 bit)
access : read-write
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