\n

SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3FC byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYSMEMREMAP

PIOPORCAP0

IOCONCLKDIV6

IOCONCLKDIV5

IOCONCLKDIV4

IOCONCLKDIV3

IOCONCLKDIV2

IOCONCLKDIV1

IOCONCLKDIV0

BODCTRL

SYSTCKCAL

IRQLATENCY

NMISRC

PINTSEL0

PINTSEL1

PINTSEL2

PINTSEL3

PINTSEL4

PINTSEL5

PINTSEL6

PINTSEL7

SYSOSCCTRL

STARTERP0

STARTERP1

PDSLEEPCFG

PDAWAKECFG

PDRUNCFG

WDTOSCCTRL

PINTSEL[0]

SYSRSTSTAT

DEVICE_ID

PRESETCTRL

SYSPLLCLKSEL

SYSPLLCLKUEN

PINTSEL[1]

PINTSEL[2]

MAINCLKSEL

MAINCLKUEN

PINTSEL[3]

SYSAHBCLKDIV

SYSPLLCTRL

SYSAHBCLKCTRL

PINTSEL[4]

UARTCLKDIV

PINTSEL[5]

SYSPLLSTAT

PINTSEL[6]

PINTSEL[7]

CLKOUTSEL

CLKOUTUEN

CLKOUTDIV

UARTFRGDIV

UARTFRGMULT

EXTTRACECMD


SYSMEMREMAP

System Remap register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSMEMREMAP SYSMEMREMAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAP

MAP : System memory remap. Value 0x3 is reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : BOOT_LOADER_MODE

Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.

0x1 : USER_RAM_MODE

User RAM Mode. Interrupt vectors are re-mapped to Static RAM.

0x2 : USER_FLASH_MODE

User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.

End of enumeration elements list.


PIOPORCAP0

POR captured PIO status 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIOPORCAP0 PIOPORCAP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOSTAT

PIOSTAT : State of PIO0_17 through PIO0_0 at power-on reset
bits : 0 - 17 (18 bit)
access : read-only


IOCONCLKDIV6

Peripheral clock 6 to the IOCON block for programmable glitch filter
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV6 IOCONCLKDIV6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV5

Peripheral clock 6 to the IOCON block for programmable glitch filter
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV5 IOCONCLKDIV5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV4

Peripheral clock 4 to the IOCON block for programmable glitch filter
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV4 IOCONCLKDIV4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV3

Peripheral clock 3 to the IOCON block for programmable glitch filter
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV3 IOCONCLKDIV3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV2

Peripheral clock 2 to the IOCON block for programmable glitch filter
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV2 IOCONCLKDIV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV1

Peripheral clock 1 to the IOCON block for programmable glitch filter
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV1 IOCONCLKDIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


IOCONCLKDIV0

Peripheral clock 0 to the IOCON block for programmable glitch filter
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCONCLKDIV0 IOCONCLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


BODCTRL

BOD control register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODCTRL BODCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BODRSTLEV BODINTVAL BODRSTENA

BODRSTLEV : BOD reset level
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x1 : LEVEL_1

Level 1

0x2 : LEVEL_2

Level 2

0x3 : LEVEL_3

Level 3

End of enumeration elements list.

BODINTVAL : BOD interrupt level
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x1 : LEVEL_1

Level 1

0x2 : LEVEL_2

Level 2

0x3 : LEVEL_3

Level 3

End of enumeration elements list.

BODRSTENA : BOD reset enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable reset function.

0x1 : ENABLE

Enable reset function.

End of enumeration elements list.


SYSTCKCAL

System tick timer calibration register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSTCKCAL SYSTCKCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL

CAL : System tick timer calibration value.
bits : 0 - 25 (26 bit)
access : read-write


IRQLATENCY

IRQ latency register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQLATENCY IRQLATENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY

LATENCY : 8-bit latency value.
bits : 0 - 7 (8 bit)
access : read-write


NMISRC

NMI source selection register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMISRC NMISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQN NMIEN

IRQN : The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1
bits : 0 - 4 (5 bit)
access : read-write

NMIEN : Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
bits : 31 - 31 (1 bit)
access : read-write


PINTSEL0

Pin interrupt select registers N
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL0 PINTSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL1

Pin interrupt select registers N
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL1 PINTSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL2

Pin interrupt select registers N
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL2 PINTSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL3

Pin interrupt select registers N
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL3 PINTSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL4

Pin interrupt select registers N
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL4 PINTSEL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL5

Pin interrupt select registers N
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL5 PINTSEL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL6

Pin interrupt select registers N
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL6 PINTSEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL7

Pin interrupt select registers N
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL7 PINTSEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
bits : 0 - 5 (6 bit)
access : read-write


SYSOSCCTRL

system oscillator control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSOSCCTRL SYSOSCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYPASS FREQRANGE

BYPASS : oscillator (Xtal) Test Mode input (Active High)
bits : 0 - 0 (1 bit)
access : read-write

FREQRANGE : oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'
bits : 1 - 1 (1 bit)
access : read-write


STARTERP0

Start logic 0 pin wake-up enable register 0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTERP0 STARTERP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PINT0 PINT1 PINT2 PINT3 PINT4 PINT5 PINT6 PINT7

PINT0 : GPIO pin interrupt 0 wake-up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT1 : GPIO pin interrupt 1 wake-up
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT2 : GPIO pin interrupt 2 wake-up
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT3 : GPIO pin interrupt 3 wake-up
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT4 : GPIO pin interrupt 4 wake-up
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT5 : GPIO pin interrupt 5 wake-up
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT6 : GPIO pin interrupt 6 wake-up
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

PINT7 : GPIO pin interrupt 7 wake-up
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


STARTERP1

Start logic 0 pin wake-up enable register 1
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTERP1 STARTERP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0 SPI1 USART0 USART1 USART2 I2C0 WWDT BOD WKT

SPI0 : SPI0 interrupt wake-up
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

SPI1 : SPI1 interrupt wake-up
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

USART0 : USART0 interrupt wake-up. Configure USART in synchronous slave mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

USART1 : USART1 interrupt wake-up. Configure USART in synchronous slave mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

USART2 : USART2 interrupt wake-up. Configure USART in synchronous slave mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

I2C0 : I2C0 interrupt wake-up.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

WWDT : WWDT interrupt wake-up
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

BOD : BOD interrupt wake-up
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

WKT : Self-wake-up timer interrupt wake-up
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


PDSLEEPCFG

Deep-sleep configuration register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDSLEEPCFG PDSLEEPCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOD_PD WDTOSC_PD

BOD_PD : BOD power-down control for Deep-sleep and Power-down mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

WDTOSC_PD : Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


PDAWAKECFG

Wake-up configuration register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDAWAKECFG PDAWAKECFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRCOUT_PD IRC_PD FLASH_PD BOD_PD SYSOSC_PD WDTOSC_PD SYSPLL_PD ACMP

IRCOUT_PD : IRC oscillator output wake-up configuration
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

IRC_PD : IRC oscillator power-down wake-up configuration
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

FLASH_PD : Flash wake-up configuration
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

BOD_PD : BOD wake-up configuration
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

SYSOSC_PD : Crystal oscillator wake-up configuration
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

WDTOSC_PD : Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

SYSPLL_PD : System PLL wake-up configuration
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

ACMP : Analog comparator wake-up configuration
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


PDRUNCFG

Power configuration register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDRUNCFG PDRUNCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRCOUT_PD IRC_PD FLASH_PD BOD_PD SYSOSC_PD WDTOSC_PD SYSPLL_PD ACMP

IRCOUT_PD : IRC oscillator output wake-up configuration
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

IRC_PD : IRC oscillator power-down wake-up configuration
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

FLASH_PD : Flash wake-up configuration
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

BOD_PD : BOD wake-up configuration
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

SYSOSC_PD : Crystal oscillator wake-up configuration
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : POWERED

powered

0x1 : POWERED_DOWN

powered down

End of enumeration elements list.

WDTOSC_PD : Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

SYSPLL_PD : System PLL wake-up configuration
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.

ACMP : Analog comparator wake-up configuration
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Disabled

0x1 : ENABLED

Enabled

End of enumeration elements list.


WDTOSCCTRL

Watchdog oscillator control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTOSCCTRL WDTOSCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVSEL FREQSEL

DIVSEL : Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
bits : 0 - 4 (5 bit)
access : read-write

FREQSEL : Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz
bits : 5 - 8 (4 bit)
access : read-write


PINTSEL[0]

Pin interrupt select registers N
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[0] PINTSEL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


SYSRSTSTAT

System reset status register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSRSTSTAT SYSRSTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR EXTRST WDT BOD SYSRST

POR : POR reset status.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : POR_0

No POR detected.

0x1 : POR_1

POR detected. Writing a one clears this reset.

End of enumeration elements list.

EXTRST : Status of the external RESET pin. External reset status.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : EXTRST_0

No reset event detected.

0x1 : EXTRST_1

Reset detected. Writing a one clears this reset.

End of enumeration elements list.

WDT : Status of the Watchdog reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : WDT_0

No WDT reset detected.

0x1 : WDT_1

WDT reset detected. Writing a one clears this reset.

End of enumeration elements list.

BOD : Status of the Brown-out detect reset.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : BOD_0

No BOD reset detected.

0x1 : BOD_1

BOD reset detected. Writing a one clears this reset.

End of enumeration elements list.

SYSRST : Status of the software system reset.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : SYSRST_0

No System reset detected.

0x1 : SYSRST_1

System reset detected. Writing a one clears this reset.

End of enumeration elements list.


DEVICE_ID

Part ID register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_ID DEVICE_ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICEID

DEVICEID : Part ID
bits : 0 - 31 (32 bit)
access : read-only


PRESETCTRL

Peripheral reset control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESETCTRL PRESETCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0_RST_N SPI1_RST_N UARTFRG_RST_N UART0_RST_N UART1_RST_N UART2_RST_N I2C0_RST_N MRT_RST_N SCT_RST_N WKT_RST_N GPIO_RST_N FLASH_RST_N ACMP_RST_N

SPI0_RST_N : SPI0 reset control.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : SPI0_RST_N_0

Assert the SPI0 reset.

0x1 : SPI0_RST_N_1

Clear the SPI0 reset.

End of enumeration elements list.

SPI1_RST_N : SPI1 reset control.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SPI1_RST_N_0

Assert the SPI1 reset.

0x1 : SPI1_RST_N_1

Clear the SPI1 reset.

End of enumeration elements list.

UARTFRG_RST_N : USART fractional baud rate generator(UARTFRG) reset control.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UARTFRG_RST_N_0

Assert the UARTFRG reset.

0x1 : UARTFRG_RST_N_1

Clear the UARTFRG reset.

End of enumeration elements list.

UART0_RST_N : USART0 reset control.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UART0_RST_N_0

Assert the USART0 reset.

0x1 : UART0_RST_N_1

Clear the USART0 reset.

End of enumeration elements list.

UART1_RST_N : USART1 reset control.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : UART1_RST_N_0

Assert the USART1 reset.

0x1 : UART1_RST_N_1

Clear the USART1 reset.

End of enumeration elements list.

UART2_RST_N : USART2 reset control.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : UART2_RST_N_0

Assert the USART2 reset.

0x1 : UART2_RST_N_1

Clear the USART2 reset.

End of enumeration elements list.

I2C0_RST_N : I2C0 reset control.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : I2C0_RST_N_0

Assert the I2C0 reset.

0x1 : I2C0_RST_N_1

Clear the I2C0 reset.

End of enumeration elements list.

MRT_RST_N : Multi-rate timer (MRT) reset control.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : MRT_RST_N_0

Assert the MRT reset.

0x1 : MRT_RST_N_1

Clear the MRT reset.

End of enumeration elements list.

SCT_RST_N : SCT reset control.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SCT_RST_N_0

Assert the SCT reset.

0x1 : SCT_RST_N_1

Clear the SCT reset.

End of enumeration elements list.

WKT_RST_N : Self-wake-up timer (WKT) reset control.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : WKT_RST_N_0

Assert the WKT reset.

0x1 : WKT_RST_N_1

Clear the WKT reset.

End of enumeration elements list.

GPIO_RST_N : GPIO and GPIO pin interrupt reset control.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : GPIO_RST_N_0

Assert the GPIO reset.

0x1 : GPIO_RST_N_1

Clear the GPIO reset.

End of enumeration elements list.

FLASH_RST_N : Flash controller reset control.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : FLASH_RST_N_0

Assert the flash controller reset.

0x1 : FLASH_RST_N_1

Clear the flash controller reset.

End of enumeration elements list.

ACMP_RST_N : Analog comparator reset control.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : ACMP_RST_N_0

Assert the analog comparator reset.

0x1 : ACMP_RST_N_1

Clear the analog comparator controller reset.

End of enumeration elements list.


SYSPLLCLKSEL

System PLL clock source select register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLCLKSEL SYSPLLCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : System PLL clock source
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : IRC

IRC

0x1 : SYSOSC

Crystal Oscillator (SYSOSC)

0x3 : CLKIN

CLKIN. External clock input.

End of enumeration elements list.


SYSPLLCLKUEN

System PLL clock source update enable register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLCLKUEN SYSPLLCLKUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA

ENA : Enable system PLL clock source update
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : NO_CHANGE

no change

0x1 : UPDATED

update clock source

End of enumeration elements list.


PINTSEL[1]

Pin interrupt select registers N
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[1] PINTSEL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL[2]

Pin interrupt select registers N
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[2] PINTSEL[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


MAINCLKSEL

Main clock source select
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAINCLKSEL MAINCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Clock source for main clock.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : IRC

IRC Oscillator.

0x1 : PLL_input

PLL input.

0x2 : Watchdog

Watchdog oscillator.

0x3 : PLL_output

PLL output.

0 : SEL_0

IRC Oscillator.

0x1 : SEL_1

PLL input.

0x2 : SEL_2

Watchdog oscillator.

0x3 : SEL_3

PLL output.

End of enumeration elements list.


MAINCLKUEN

Main clock source update enable
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAINCLKUEN MAINCLKUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA

ENA : Enable main clock source update.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ENA_0

No change.

0x1 : ENA_1

Update clock source.

End of enumeration elements list.


PINTSEL[3]

Pin interrupt select registers N
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[3] PINTSEL[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


SYSAHBCLKDIV

System clock divider
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSAHBCLKDIV SYSAHBCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


SYSPLLCTRL

PLL control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSPLLCTRL SYSPLLCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL PSEL

MSEL : Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32
bits : 0 - 4 (5 bit)
access : read-write

PSEL : Post divider ratio P. The division ratio is 2 x P.
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : PSEL_0

P = 1

0x1 : PSEL_1

P = 2

0x2 : PSEL_2

P = 4

0x3 : PSEL_3

P = 8

End of enumeration elements list.


SYSAHBCLKCTRL

System clock control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSAHBCLKCTRL SYSAHBCLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS ROM RAM0_1 FLASHREG FLASH I2C0 GPIO SWM SCT WKT MRT SPI0 SPI1 CRC UART0 UART1 UART2 WWDT IOCON ACMP

SYS : Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.
bits : 0 - 0 (1 bit)
access : read-write

ROM : Enables clock for ROM.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : ROM_0

Disable.

0x1 : ROM_1

Enable.

End of enumeration elements list.

RAM0_1 : Enables clock for SRAM0 and SRAM1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : RAM0_1_0

Disable.

0x1 : RAM0_1_1

Enable.

End of enumeration elements list.

FLASHREG : Enables clock for flash register interface.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : FLASHREG_0

Disable.

0x1 : FLASHREG_1

Enable.

End of enumeration elements list.

FLASH : Enables clock for flash.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : FLASH_0

Disable.

0x1 : FLASH_1

Enable.

End of enumeration elements list.

I2C0 : Enables clock for I2C0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : I2C0_0

Disable.

0x1 : I2C0_1

Enable.

End of enumeration elements list.

GPIO : Enables clock for GPIO port registers and GPIO pin interrupt registers.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : GPIO_0

Disable.

0x1 : GPIO_1

Enable.

End of enumeration elements list.

SWM : Enables clock for switch matrix.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : SWM_0

Disable.

0x1 : SWM_1

Enable.

End of enumeration elements list.

SCT : Enables clock for state configurable timer SCTimer/PWM.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : SCT_0

Disable.

0x1 : SCT_1

Enable.

End of enumeration elements list.

WKT : Enables clock for self-wake-up timer.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : WKT_0

Disable.

0x1 : WKT_1

Enable.

End of enumeration elements list.

MRT : Enables clock for multi-rate timer.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : MRT_0

Disable.

0x1 : MRT_1

Enable.

End of enumeration elements list.

SPI0 : Enables clock for SPI0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SPI0_0

Disable.

0x1 : SPI0_1

Enable.

End of enumeration elements list.

SPI1 : Enables clock for SPI1.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : SPI1_0

Disable.

0x1 : SPI1_1

Enable.

End of enumeration elements list.

CRC : Enables clock for CRC.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : CRC_0

Disable.

0x1 : CRC_1

Enable.

End of enumeration elements list.

UART0 : Enables clock for USART0.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : UART0_0

Disable.

0x1 : UART0_1

Enable.

End of enumeration elements list.

UART1 : Enables clock for USART1.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : UART1_0

Disable.

0x1 : UART1_1

Enable.

End of enumeration elements list.

UART2 : Enables clock for USART2.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : UART2_0

Disable.

0x1 : UART2_1

Enable.

End of enumeration elements list.

WWDT : Enables clock for WWDT.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : WWDT_0

Disable.

0x1 : WWDT_1

Enable.

End of enumeration elements list.

IOCON : Enables clock for IOCON block.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : IOCON_0

Disable.

0x1 : IOCON_1

Enable.

End of enumeration elements list.

ACMP : Enables clock to analog comparator.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : ACMP_0

Disable.

0x1 : ACMP_1

Enable.

End of enumeration elements list.


PINTSEL[4]

Pin interrupt select registers N
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[4] PINTSEL[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


UARTCLKDIV

USART clock divider
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTCLKDIV UARTCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.
bits : 0 - 7 (8 bit)
access : read-write


PINTSEL[5]

Pin interrupt select registers N
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[5] PINTSEL[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


SYSPLLSTAT

PLL status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYSPLLSTAT SYSPLLSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : PLL0 lock indicator
bits : 0 - 0 (1 bit)
access : read-only


PINTSEL[6]

Pin interrupt select registers N
address_offset : 0xC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[6] PINTSEL[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


PINTSEL[7]

Pin interrupt select registers N
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINTSEL[7] PINTSEL[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTPIN

INTPIN : Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
bits : 0 - 5 (6 bit)
access : read-write


CLKOUTSEL

CLKOUT clock source select
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTSEL CLKOUTSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : CLKOUT clock source.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : IRC

IRC oscillator

0x1 : SYSOSC

Crystal oscillator (SYSOSC)

0x2 : Watchdog

Watchdog oscillator

0x3 : main_clk

Main clock

0 : SEL_0

IRC oscillator

0x1 : SEL_1

Crystal oscillator (SYSOSC)

0x2 : SEL_2

Watchdog oscillator

0x3 : SEL_3

Main clock

End of enumeration elements list.


CLKOUTUEN

CLKOUT clock source update enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTUEN CLKOUTUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENA

ENA : Enable CLKOUT clock source update.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ENA_0

No change

0x1 : ENA_1

Update clock source

End of enumeration elements list.


CLKOUTDIV

PLL control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKOUTDIV CLKOUTDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : CLKOUT clock divider values. 0: Disable CLKOUT clock divider 1: Divide by 1 to 255: Divide by 255
bits : 0 - 7 (8 bit)
access : read-write


UARTFRGDIV

USART1 to USART4 common fractional generator divider value
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTFRGDIV UARTFRGDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
bits : 0 - 7 (8 bit)
access : read-write


UARTFRGMULT

USART1 to USART4 common fractional generator divider value
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UARTFRGMULT UARTFRGMULT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MULT

MULT : Numerator of the fractional divider. MULT is equal to the programmed value.
bits : 0 - 7 (8 bit)
access : read-write


EXTTRACECMD

External trace buffer command register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTTRACECMD EXTTRACECMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP

START : Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well.
bits : 0 - 0 (1 bit)
access : read-write

STOP : Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well.
bits : 1 - 1 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.