Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
SPI Configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SPI enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0x1 : ENABLED
Enabled. The SPI is enabled for operation.
End of enumeration elements list.
MASTER : Master mode select.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0x1 : MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
End of enumeration elements list.
LSBF : LSB First mode enable.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0x1 : REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
End of enumeration elements list.
CPHA : Clock Phase select.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0x1 : CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
End of enumeration elements list.
CPOL : Clock Polarity select.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The rest state of the clock (between transfers) is low.
0x1 : HIGH
High. The rest state of the clock (between transfers) is high.
End of enumeration elements list.
LOOP : Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled.
0x1 : ENABLED
Enabled.
End of enumeration elements list.
SPOL0 : SSEL0 Polarity select.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL0 pin is active low.
0x1 : HIGH
High. The SSEL0 pin is active high.
End of enumeration elements list.
SPOL1 : SSEL1 Polarity select.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL1 pin is active low.
0x1 : HIGH
High. The SSEL1 pin is active high.
End of enumeration elements list.
SPOL2 : SSEL2 Polarity select.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL2 pin is active low.
0x1 : HIGH
High. The SSEL2 pin is active high.
End of enumeration elements list.
SPOL3 : SSEL3 Polarity select.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : LOW
Low. The SSEL3 pin is active low.
0x1 : HIGH
High. The SSEL3 pin is active high.
End of enumeration elements list.
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDYEN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 0 - 0 (1 bit)
access : write-only
TXRDYEN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 1 - 1 (1 bit)
access : write-only
RXOVEN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 2 - 2 (1 bit)
access : write-only
TXUREN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 3 - 3 (1 bit)
access : write-only
SSAEN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 4 - 4 (1 bit)
access : write-only
SSDEN : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 5 - 5 (1 bit)
access : write-only
MSTIDLE : Writing 1 clears the corresponding bits in the INTENSET register.
bits : 8 - 8 (1 bit)
access : write-only
SPI Receive Data
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
bits : 0 - 15 (16 bit)
access : read-only
RXSSEL0_N : Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 16 - 16 (1 bit)
access : read-only
RXSSEL1_N : Slave Select for receive. This field allows the state of the SSEL1 pin to be saved along with received data. The value will reflect the SSEL1 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 17 - 17 (1 bit)
access : read-only
RXSSEL2_N : Slave Select for receive. This field allows the state of the SSEL2 pin to be saved along with received data. The value will reflect the SSEL2 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 18 - 18 (1 bit)
access : read-only
RXSSEL3_N : Slave Select for receive. This field allows the state of the SSEL3 pin to be saved along with received data. The value will reflect the SSEL3 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
bits : 19 - 19 (1 bit)
access : read-only
SOT : Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
bits : 20 - 20 (1 bit)
access : read-only
SPI Transmit Data with Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDAT : Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
bits : 0 - 15 (16 bit)
access : read-write
TXSSEL0_N : Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TXSSEL0_N_0
SSEL0 asserted.
0x1 : TXSSEL0_N_1
SSEL0 not asserted.
End of enumeration elements list.
TXSSEL1_N : Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TXSSEL1_N_0
SSEL1 asserted.
0x1 : TXSSEL1_N_1
SSEL1 not asserted.
End of enumeration elements list.
TXSSEL2_N : Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TXSSEL2_N_0
SSEL2 asserted.
0x1 : TXSSEL2_N_1
SSEL2 not asserted.
End of enumeration elements list.
TXSSEL3_N : Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : TXSSEL3_N_0
SSEL3 asserted.
0x1 : TXSSEL3_N_1
SSEL3 not asserted.
End of enumeration elements list.
EOT : End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : SSEL_deasserted
This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0x1 : SSEL_not_deasserted
This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
End of enumeration elements list.
EOF : End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : Data_not_EOF
This piece of data transmitted is not treated as the end of a frame.
0x1 : Data_EOF
This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
End of enumeration elements list.
RXIGNORE : Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : Read_received_data
Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0x1 : Ignore_received_data
Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
End of enumeration elements list.
LEN : Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : LEN_0
no description available
0x1 : LEN_1
Data transfer is 1 bit in length.
0x2 : LEN_2
Data transfer is 2 bit in length.
0x3 : LEN_3
Data transfer is 3 bit in length.
0x4 : LEN_4
Data transfer is 4 bit in length.
0x5 : LEN_5
Data transfer is 5 bit in length.
0x6 : LEN_6
Data transfer is 6 bit in length.
0x7 : LEN_7
Data transfer is 7 bit in length.
0x8 : LEN_8
Data transfer is 8 bit in length.
0x9 : LEN_9
Data transfer is 9 bit in length.
0xA : LEN_10
Data transfer is 10 bit in length.
0xB : LEN_11
Data transfer is 11 bit in length.
0xC : LEN_12
Data transfer is 12 bit in length.
0xD : LEN_13
Data transfer is 13 bit in length.
0xE : LEN_14
Data transfer is 14 bit in length.
0xF : LEN_15
Data transfer is 15 bit in length.
End of enumeration elements list.
SPI Transmit Data.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
bits : 0 - 15 (16 bit)
access : read-write
SPI Transmit Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSSEL0_N : Transmit Slave Select 0.
bits : 16 - 16 (1 bit)
access : read-write
TXSSEL1_N : Transmit Slave Select 1.
bits : 17 - 17 (1 bit)
access : read-write
TXSSEL2_N : Transmit Slave Select 2.
bits : 18 - 18 (1 bit)
access : read-write
TXSSEL3_N : Transmit Slave Select 3.
bits : 19 - 19 (1 bit)
access : read-write
EOT : End of Transfer.
bits : 20 - 20 (1 bit)
access : read-write
EOF : End of Frame.
bits : 21 - 21 (1 bit)
access : read-write
RXIGNORE : Receive Ignore.
bits : 22 - 22 (1 bit)
access : read-write
LEN : Data transfer Length.
bits : 24 - 27 (4 bit)
access : read-write
SPI clock Divider
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVVAL : Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
bits : 0 - 15 (16 bit)
access : read-write
SPI Interrupt Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready flag.
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready flag.
bits : 1 - 1 (1 bit)
access : read-only
RXOV : Receiver Overrun interrupt flag.
bits : 2 - 2 (1 bit)
access : read-only
TXUR : Transmitter Underrun interrupt flag.
bits : 3 - 3 (1 bit)
access : read-only
SSA : Slave Select Assert.
bits : 4 - 4 (1 bit)
access : read-only
SSD : Slave Select Deassert.
bits : 5 - 5 (1 bit)
access : read-only
MSTIDLE : Master Idle status flag.
bits : 8 - 8 (1 bit)
access : read-only
SPI Delay register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE_DELAY : Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 0 - 3 (4 bit)
access : read-write
POST_DELAY : Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 4 - 7 (4 bit)
access : read-write
FRAME_DELAY : If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
bits : 8 - 11 (4 bit)
access : read-write
TRANSFER_DELAY : Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
bits : 12 - 15 (4 bit)
access : read-write
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
bits : 1 - 1 (1 bit)
access : read-only
RXOV : Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
bits : 2 - 2 (1 bit)
access : write-only
TXUR : Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
bits : 3 - 3 (1 bit)
access : write-only
SSA : Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
bits : 4 - 4 (1 bit)
access : write-only
SSD : Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
bits : 5 - 5 (1 bit)
access : write-only
STALLED : Stalled status flag. This indicates whether the SPI is currently in a stall condition.
bits : 6 - 6 (1 bit)
access : read-only
ENDTRANSFER : End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
bits : 7 - 7 (1 bit)
access : read-write
MSTIDLE : Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
bits : 8 - 8 (1 bit)
access : read-only
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDYEN : Determines whether an interrupt occurs when receiver data is available.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : RXRDYEN_0
No interrupt will be generated when receiver data is available.
0x1 : RXRDYEN_1
An interrupt will be generated when receiver data is available in the RXDAT register.
End of enumeration elements list.
TXRDYEN : Determines whether an interrupt occurs when the transmitter holding register is available.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TXRDYEN_0
No interrupt will be generated when the transmitter holding register is available.
0x1 : TXRDYEN_1
An interrupt will be generated when data may be written to TXDAT.
End of enumeration elements list.
RXOVEN : Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : RXOVEN_0
No interrupt will be generated when a receiver overrun occurs.
0x1 : RXOVEN_1
An interrupt will be generated if a receiver overrun occurs.
End of enumeration elements list.
TXUREN : Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TXUREN_0
No interrupt will be generated when the transmitter underruns.
0x1 : TXUREN_1
An interrupt will be generated if the transmitter underruns.
End of enumeration elements list.
SSAEN : Determines whether an interrupt occurs when the Slave Select is asserted.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : SSAEN_0
No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1 : SSAEN_1
An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
End of enumeration elements list.
SSDEN : Determines whether an interrupt occurs when the Slave Select is deasserted.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : SSDEN_0
No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1 : SSDEN_1
An interrupt will be generated when all asserted Slave Selects transition to deasserted.
End of enumeration elements list.
MSTIDLEEN : Determines whether an interrupt occurs when the MSTIDLE enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : MSTIDLEEN_0
No interrupt will be generated when MSTIDLE enabled.
0x1 : MSTIDLEEN_1
An interrupt will be generated when MSTIDLE enabled.
End of enumeration elements list.
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