Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-INTVAL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TIMER
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CTRL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-STAT
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-INTVAL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TIMER
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-STAT
MRT Time interval value register. This value is loaded into the TIMER register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 30 (31 bit)
access : read-write
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
End of enumeration elements list.
MRT Time interval value register. This value is loaded into the TIMER register.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 30 (31 bit)
access : read-write
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
End of enumeration elements list.
MRT Timer register. This register reads the value of the down-counter.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 30 (31 bit)
access : read-only
MRT Control register. This register controls the MRT modes.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. TIMERn interrupt is disabled.
0x1 : ENABLED
Enabled. TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
End of enumeration elements list.
MRT Status register.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0x1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IDLE_STATE
Idle state. TIMERn is stopped.
0x1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
MRT Time interval value register. This value is loaded into the TIMER register.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 30 (31 bit)
access : read-write
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
End of enumeration elements list.
MRT Timer register. This register reads the value of the down-counter.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 30 (31 bit)
access : read-only
MRT Control register. This register controls the MRT modes.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. TIMERn interrupt is disabled.
0x1 : ENABLED
Enabled. TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
End of enumeration elements list.
MRT Status register.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0x1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IDLE_STATE
Idle state. TIMERn is stopped.
0x1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
MRT Timer register. This register reads the value of the down-counter.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 30 (31 bit)
access : read-only
MRT Time interval value register. This value is loaded into the TIMER register.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVALUE : Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
bits : 0 - 30 (31 bit)
access : read-write
LOAD : Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0x1 : FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
End of enumeration elements list.
MRT Timer register. This register reads the value of the down-counter.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALUE : Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
bits : 0 - 30 (31 bit)
access : read-only
MRT Control register. This register controls the MRT modes.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. TIMERn interrupt is disabled.
0x1 : ENABLED
Enabled. TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
End of enumeration elements list.
MRT Status register.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0x1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IDLE_STATE
Idle state. TIMERn is stopped.
0x1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
MRT Control register. This register controls the MRT modes.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Enable the TIMERn interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Disabled. TIMERn interrupt is disabled.
0x1 : ENABLED
Enabled. TIMERn interrupt is enabled.
End of enumeration elements list.
MODE : Selects timer mode.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0x1 : ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x2 : ONE_SHOT_STALL_MODE
One-shot stall mode.
End of enumeration elements list.
MRT Status register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTFLAG : Monitors the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0x1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
End of enumeration elements list.
RUN : Indicates the state of TIMERn. This bit is read-only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : IDLE_STATE
Idle state. TIMERn is stopped.
0x1 : RUNNING
Running. TIMERn is running.
End of enumeration elements list.
Module Configuration register. This register provides information about this particular MRT instance.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOC : Identifies the number of channels in this MRT.(4 channels on this device.)
bits : 0 - 3 (4 bit)
access : read-only
NOB : Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
bits : 4 - 8 (5 bit)
access : read-only
Idle channel register. This register returns the number of the first idle channel.
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN : Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
bits : 4 - 7 (4 bit)
access : read-only
Global interrupt flag register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GFLAG0 : Monitors the interrupt flag of TIMER0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0x1 : PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
End of enumeration elements list.
GFLAG1 : Monitors the interrupt flag of TIMER1. See description of channel 0.
bits : 1 - 1 (1 bit)
access : read-write
GFLAG2 : Monitors the interrupt flag of TIMER2. See description of channel 0.
bits : 2 - 2 (1 bit)
access : read-write
GFLAG3 : Monitors the interrupt flag of TIMER3. See description of channel 0.
bits : 3 - 3 (1 bit)
access : read-write
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