Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : USART Enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available.
1 : ENABLED
Enabled. The USART is enabled for operation.
End of enumeration elements list.
DATALEN : Selects the data size for the USART.
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0x0 : 7_BIT_DATA_LENGTH
7 bit Data length.
0x1 : 8_BIT_DATA_LENGTH
8 bit Data length.
0x2 : 9_BIT_DATA_LENGTH
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x3 : RESERVED
Reserved.
End of enumeration elements list.
PARITYSEL : Selects what type of parity is used by the USART.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0x0 : NO_PARITY
No parity.
0x1 : RESERVED
Reserved.
0x2 : EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x3 : ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
End of enumeration elements list.
STOPLEN : Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : 1_STOP_BIT
1 stop bit.
1 : 2_STOP_BITS
2 stop bits. This setting should only be used for asynchronous communication.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 15 (9 bit)
CTSEN : CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NO_FLOW_CONTROL
No flow control. The transmitter does not receive any automatic flow control signal.
1 : FLOW_CONTROL_ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 20 (11 bit)
SYNCEN : Selects synchronous or asynchronous operation.
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : ASYNCHRONOUS_MODE_IS
Asynchronous mode is selected.
1 : SYNCHRONOUS_MODE_IS
Synchronous mode is selected.
End of enumeration elements list.
CLKPOL : Selects the clock polarity and sampling edge of received data in synchronous mode.
bits : 12 - 24 (13 bit)
Enumeration: ENUM
0 : FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
1 : RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 13 - 26 (14 bit)
SYNCMST : Synchronous mode Master select.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
1 : MASTER
Master. When synchronous mode is enabled, the USART is a master.
End of enumeration elements list.
LOOP : Selects data loopback mode.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : NORMAL_OPERATION
Normal operation.
1 : LOOPBACK_MODE
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 33 (18 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 33 (18 bit)
OETA : Output Enable Turnaround time enable for RS-485 operation.
bits : 18 - 36 (19 bit)
Enumeration: ENUM
0 : DEASSERTED
Deasserted. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
1 : ASSERTED
Asserted. If selected by OESEL, the Output Enable signal remains asserted for 1 character time after then end the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.
End of enumeration elements list.
AUTOADDR : Automatic Address matching enable.
bits : 19 - 38 (20 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).
1 : ENABLED
Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.
End of enumeration elements list.
OESEL : Output Enable Select.
bits : 20 - 40 (21 bit)
Enumeration: ENUM
0 : FLOW_CONTROL
Flow control. The RTS signal is used as the standard flow control function.
1 : OUTPUT_ENABLE
Output enable. The RTS signal is taken over in order to provide an output enable signal to control an RS-485 transceiver.
End of enumeration elements list.
OEPOL : Output Enable Polarity.
bits : 21 - 42 (22 bit)
Enumeration: ENUM
0 : LOW
Low. If selected by OESEL, the output enable is active low.
1 : HIGH
High. If selected by OESEL, the output enable is active high.
End of enumeration elements list.
RXPOL : Receive data polarity.
bits : 22 - 44 (23 bit)
Enumeration: ENUM
0 : NOT_CHANGED
Not changed. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
1 : INVERTED
Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
End of enumeration elements list.
TXPOL : Transmit data polarity.
bits : 23 - 46 (24 bit)
Enumeration: ENUM
0 : NOT_CHANGED
Not changed. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.
1 : INVERTED
Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 24 - 55 (32 bit)
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDYCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 0 - 0 (1 bit)
TXRDYCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 2 - 4 (3 bit)
TXIDLECLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 3 - 6 (4 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 8 (5 bit)
DELTACTSCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 5 - 10 (6 bit)
TXDISINTCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 6 - 12 (7 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
OVERRUNCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 8 - 16 (9 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
DELTARXBRKCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 11 - 22 (12 bit)
STARTCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 12 - 24 (13 bit)
FRAMERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 13 - 26 (14 bit)
PARITYERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 14 - 28 (15 bit)
RXNOISECLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 15 - 30 (16 bit)
ABERRCLR : Writing 1 clears the corresponding bit in the INTENSET register.
bits : 16 - 32 (17 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
Receiver Data register. Contains the last character received.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
bits : 0 - 8 (9 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 9 - 40 (32 bit)
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
bits : 0 - 8 (9 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 9 - 21 (13 bit)
FRAMERR : Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
bits : 13 - 26 (14 bit)
PARITYERR : Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
bits : 14 - 28 (15 bit)
RXNOISE : Received Noise flag. See description of the RXNOISEINT bit in Table 177.
bits : 15 - 30 (16 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 16 - 47 (32 bit)
Transmit Data register. Data to be transmitted is written here.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDAT : Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
bits : 0 - 8 (9 bit)
RESERVED : Reserved. Only zero should be written.
bits : 9 - 40 (32 bit)
Baud Rate Generator register. 16-bit integer baud rate divisor value.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRGVAL : This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function.
bits : 0 - 15 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 16 - 47 (32 bit)
Interrupt status register. Reflects interrupts that are currently enabled.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready flag.
bits : 0 - 0 (1 bit)
TXRDY : Transmitter Ready flag.
bits : 2 - 4 (3 bit)
TXIDLE : Transmitter idle status.
bits : 3 - 6 (4 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 8 (5 bit)
DELTACTS : This bit is set when a change in the state of the CTS input is detected.
bits : 5 - 10 (6 bit)
TXDISINT : Transmitter Disabled Interrupt flag.
bits : 6 - 12 (7 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
OVERRUNINT : Overrun Error interrupt flag.
bits : 8 - 16 (9 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
DELTARXBRK : This bit is set when a change in the state of receiver break detection occurs.
bits : 11 - 22 (12 bit)
START : This bit is set when a start is detected on the receiver input.
bits : 12 - 24 (13 bit)
FRAMERRINT : Framing Error interrupt flag.
bits : 13 - 26 (14 bit)
PARITYERRINT : Parity Error interrupt flag.
bits : 14 - 28 (15 bit)
RXNOISEINT : Received Noise interrupt flag.
bits : 15 - 30 (16 bit)
ABERR : Autobaud Error flag.
bits : 16 - 32 (17 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
Oversample selection register for asynchronous communication.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSRVAL : Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 peripheral clocks are used to transmit and receive each data bit. 0x5 = 6 peripheral clocks are used to transmit and receive each data bit. ... 0xF= 16 peripheral clocks are used to transmit and receive each data bit.
bits : 0 - 3 (4 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 4 - 35 (32 bit)
Address register for automatic address matching.
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : 8-bit address used with automatic address matching. Used when address detection is enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
bits : 0 - 7 (8 bit)
RESERVED : Reserved, the value read from a reserved bit is not defined.
bits : 8 - 39 (32 bit)
USART Control register. USART control settings that are more likely to change during operation.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBRKEN : Break Enable.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NORMAL_OPERATION
Normal operation.
1 : CONTINUOUS_BREAK_IS
Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
End of enumeration elements list.
ADDRDET : Enable address detect mode.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. The USART presents all incoming data.
1 : ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 8 (6 bit)
TXDIS : Transmit Disable.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : NOT_DISABLED
Not disabled. USART transmitter is not disabled.
1 : DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
CC : Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
1 : CONTINUOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
End of enumeration elements list.
CLRCCONRX : Clear Continuous Clock.
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_THE_CC
No effect on the CC bit.
1 : AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 25 (16 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 25 (16 bit)
AUTOBAUD : Autobaud enable.
bits : 16 - 32 (17 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. UART is in normal operating mode.
1 : ENABLED
Enabled. UART is in autobaud mode. This bit should only be set when the UART is enabled in the CFG register and the UART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. This bit can be cleared by software when set, but only when the UART receiver is idle. Disabling the UART in the CFG register also clears the AUTOBAUD bit.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
bits : 0 - 0 (1 bit)
RXIDLE : Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
bits : 1 - 2 (2 bit)
TXRDY : Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
bits : 2 - 4 (3 bit)
TXIDLE : Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
bits : 3 - 6 (4 bit)
CTS : This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
bits : 4 - 8 (5 bit)
DELTACTS : This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
bits : 5 - 10 (6 bit)
TXDISSTAT : Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
bits : 6 - 12 (7 bit)
OVERRUNINT : Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
bits : 8 - 16 (9 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 18 (10 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 18 (10 bit)
RXBRK : Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
bits : 10 - 20 (11 bit)
DELTARXBRK : This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
bits : 11 - 22 (12 bit)
START : This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
bits : 12 - 24 (13 bit)
FRAMERRINT : Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
bits : 13 - 26 (14 bit)
PARITYERRINT : Parity Error interrupt flag. This flag is set when a parity error is detected in a received character..
bits : 14 - 28 (15 bit)
RXNOISEINT : Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
bits : 15 - 30 (16 bit)
ABERR : Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the end of the start bit that is being measured, essentially an autobaud time-out.
bits : 16 - 32 (17 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRDYEN : When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
bits : 0 - 0 (1 bit)
TXRDYEN : When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
bits : 2 - 4 (3 bit)
TXIDLEEN : When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
bits : 3 - 6 (4 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 4 - 8 (5 bit)
DELTACTSEN : When 1, enables an interrupt when there is a change in the state of the CTS input.
bits : 5 - 10 (6 bit)
TXDISEN : When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
bits : 6 - 12 (7 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
OVERRUNEN : When 1, enables an interrupt when an overrun error occurred.
bits : 8 - 16 (9 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 9 - 19 (11 bit)
DELTARXBRKEN : When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
bits : 11 - 22 (12 bit)
STARTEN : When 1, enables an interrupt when a received start bit has been detected.
bits : 12 - 24 (13 bit)
FRAMERREN : When 1, enables an interrupt when a framing error has been detected.
bits : 13 - 26 (14 bit)
PARITYERREN : When 1, enables an interrupt when a parity error has been detected.
bits : 14 - 28 (15 bit)
RXNOISEEN : When 1, enables an interrupt when noise is detected.
bits : 15 - 30 (16 bit)
ABERREN : When 1, enables an interrupt when an autobaud error occurs.
bits : 16 - 32 (17 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 17 - 48 (32 bit)
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