Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
DMA control.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DMA controller master enable.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
1 : ENABLED
Enabled. The DMA controller is enabled.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 32 (32 bit)
Channel Enable read and Set for all DMA channels.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENA : Enable for DMA channels 17:0. Bit n enables or disables DMA channel n. 0 = disabled. 1 = enabled.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Channel Enable Clear for all DMA channels.
address_offset : 0x28 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Channel Active status for all DMA channels.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACT : Active flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not active. 1 = active.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Channel Busy status for all DMA channels.
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BSY : Busy flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = not busy. 1 = busy.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Interrupt status.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 0 - 0 (1 bit)
ACTIVEINT : Summarizes whether any enabled interrupts are pending.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : NOT_PENDING
Not pending. No enabled interrupts are pending.
1 : PENDING
Pending. At least one enabled interrupt is pending.
End of enumeration elements list.
ACTIVEERRINT : Summarizes whether any error interrupts are pending.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_PENDING
Not pending. No error interrupts are pending.
1 : PENDING
Pending. At least one error interrupt is pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Error Interrupt status for all DMA channels.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR : Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. 0 = error interrupt is not active. 1 = error interrupt is active.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x420 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x424 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x428 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x430 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x434 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x438 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x444 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x448 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x450 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x454 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x458 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x460 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x464 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x468 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x470 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x474 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x478 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Interrupt Enable read and Set for all DMA channels.
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN : Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. 0 = interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x480 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x484 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x488 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x490 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x494 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x498 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4A0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4A4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4A8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4B0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4B4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4B8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4C0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4C4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4C8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4D0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4D4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4D8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4E0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4E4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4E8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x4F0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x4F4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x4F8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Interrupt Enable Clear for all DMA channels.
address_offset : 0x50 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Writing ones to this register clears corresponding bits in the INTENSET0. Bit n corresponds to DMA channel n.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x500 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x504 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x508 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Configuration register for DMA channel 0.
address_offset : 0x510 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIPHREQEN : Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.This bit is reserved for channel 2, 3, 4, 5, and channels 12 to 17 since peripheral request is not available on these channels.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Peripheral DMA requests are disabled.
1 : ENABLED
Enabled. Peripheral DMA requests are enabled.
End of enumeration elements list.
HWTRIGEN : Hardware Triggering Enable for this channel.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Hardware triggering is not used.
1 : ENABLED
Enabled. Use hardware triggering.
End of enumeration elements list.
TRIGPOL : Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : ACTIVE_LOW__FALLING
Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1 : ACTIVE_HIGH__RISING
Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
End of enumeration elements list.
TRIGTYPE : Trigger Type. Selects hardware trigger as edge triggered or level triggered.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : EDGE
Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1 : LEVEL
Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.
End of enumeration elements list.
TRIGBURST : Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : SINGLE_TRANSFER
Single transfer. Hardware trigger causes a single transfer.
1 : BURST_TRANSFER
Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 7 - 14 (8 bit)
BURSTPOWER : Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). ... 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
bits : 8 - 19 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 12 - 25 (14 bit)
SRCBURSTWRAP : Source Burst Wrap. When enabled, the source data address for the DMA is wrapped, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
bits : 14 - 28 (15 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Source burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Source burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
DSTBURSTWRAP : Destination Burst Wrap. When enabled, the destination data address for the DMA is wrapped, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
bits : 15 - 30 (16 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Destination burst wrapping is not enabled for this DMA channel.
1 : ENABLED
Enabled. Destination burst wrapping is enabled for this DMA channel.
End of enumeration elements list.
CHPRIORITY : Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported. 0x0 = highest priority. 0x7 = lowest priority.
bits : 16 - 34 (19 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 19 - 50 (32 bit)
Control and status register for DMA channel 0.
address_offset : 0x514 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALIDPENDING : Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NO_EFFECT_ON_DMA_OPE
No effect on DMA operation.
1 : VALID_PENDING
Valid pending.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 1 - 2 (2 bit)
TRIG : Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOT_TRIGGERED
Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1 : TRIGGERED
Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 3 - 34 (32 bit)
Transfer configuration register for DMA channel 0.
address_offset : 0x518 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFGVALID : Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : NOT_VALID
Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1 : VALID
Valid. The current channel descriptor is considered valid.
End of enumeration elements list.
RELOAD : Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : DISABLED
Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1 : ENABLED
Enabled. Reload the channels' control structure when the current descriptor is exhausted.
End of enumeration elements list.
SWTRIG : Software Trigger.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : NOTSET
When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1 : SET
When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.
End of enumeration elements list.
CLRTRIG : Clear Trigger.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : NOT_CLEARED
Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1 : CLEARED
Cleared. The trigger is cleared when this descriptor is exhausted.
End of enumeration elements list.
SETINTA : Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
SETINTB : Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : NO_EFFECT
No effect.
1 : SET
Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
End of enumeration elements list.
WIDTH : Transfer width used for this DMA channel.
bits : 8 - 17 (10 bit)
Enumeration: ENUM
0x0 : 8_BIT_TRANSFERS_ARE
8-bit transfers are performed (8-bit source reads and destination writes).
0x1 : 16_BIT_TRANSFERS_ARE
16-bit transfers are performed (16-bit source reads and destination writes).
0x2 : 32_BIT_TRANSFERS_ARE
32-bit transfers are performed (32-bit source reads and destination writes).
0x3 : RESERVED_SETTING
Reserved setting, do not use.
End of enumeration elements list.
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 10 - 21 (12 bit)
SRCINC : Determines whether the source address is incremented for each DMA transfer.
bits : 12 - 25 (14 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.
0x2 : 2_X_WIDTH
2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
DSTINC : Determines whether the destination address is incremented for each DMA transfer.
bits : 14 - 29 (16 bit)
Enumeration: ENUM
0x0 : NO_INCREMENT
No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.
0x1 : 1_X_WIDTH
1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.
0x2 : 2_X_WIDTH
2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
0x3 : 4_X_WIDTH
4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
End of enumeration elements list.
XFERCOUNT : Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. ... 0x3FF = a total of 1,024 transfers will be performed.
bits : 16 - 41 (26 bit)
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 26 - 57 (32 bit)
Interrupt A status for all DMA channels.
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IA : Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active. 1 = the DMA channel interrupt A is active.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Interrupt B status for all DMA channels.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IB : Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Set ValidPending control bits for all DMA channels.
address_offset : 0x68 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SV : SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the VALIDPENDING control bit for DMA channel n.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Set Trigger control bits for all DMA channels.
address_offset : 0x70 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TRIG : Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = sets the TRIG bit for DMA channel n.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
Channel Abort control for all DMA channels.
address_offset : 0x78 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ABORTCTRL : Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. 1 = aborts DMA operations on channel n.
bits : 0 - 17 (18 bit)
RESERVED : Reserved.
bits : 18 - 49 (32 bit)
SRAM address of the channel configuration table.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Reserved. Read value is undefined, only zero should be written.
bits : 0 - 8 (9 bit)
OFFSET : Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the table must begin on a 512 byte boundary.
bits : 9 - 40 (32 bit)
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