\n
address_offset : 0x0 Bytes (0x0)
size : 0xE0 byte (0x0)
mem_usage : registers
protection : not protected
Digital I/O control for pins PIO0_17
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
DACMODE : DAC mode enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLE
Enable.
End of enumeration elements list.
Digital I/O control for port 0 pins PIO0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
DACMODE : DAC mode enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLE
Enable.
End of enumeration elements list.
Digital I/O control for pins PIO0_4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_11
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0x1 : Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2 : FAST_PLUS_I2C
Fast-mode Plus I2C
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0x1 : Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2 : FAST_PLUS_I2C
Fast-mode Plus I2C
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_10
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0x1 : Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2 : FAST_PLUS_I2C
Fast-mode Plus I2C
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0x1 : Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x2 : FAST_PLUS_I2C
Fast-mode Plus I2C
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_16
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_15
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_9
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_8
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_13
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_6
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_14
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_28
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_27
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_26
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_25
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_23
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_22
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_21
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_20
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_19
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_18
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_8
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_12
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_9
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO32
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_12
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO33
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_13
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO34
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_31
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO35
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO36
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO37
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO38
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_14
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO39
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_15
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO40
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO41
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO42
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO43
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_16
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO44
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_17
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO45
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_6
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO46
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_18
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO47
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_5
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 0 pins PIO3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_19
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO48
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_7
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO49
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_29
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO50
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO0_30
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO51
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_20
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO52
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_21
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO53
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_11
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO54
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for pins PIO1_10
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
Digital I/O control for port 1 pins PIO55
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0 : INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0x1 : PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x2 : PULL_UP
Pull-up. Pull-up resistor enabled.
0x3 : REPEATER
Repeater. Repeater mode.
End of enumeration elements list.
HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable
0x1 : ENABLE
Enable
End of enumeration elements list.
INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0x1 : INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
End of enumeration elements list.
OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable.
0x1 : ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
End of enumeration elements list.
S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0 : S_MODE_0
Bypass input filter.
0x1 : S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x2 : S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x3 : S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
End of enumeration elements list.
CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : CLK_DIV_0
IOCONCLKDIV0
0x1 : CLK_DIV_1
IOCONCLKDIV1
0x2 : CLK_DIV_2
IOCONCLKDIV2
0x3 : CLK_DIV_3
IOCONCLKDIV3
0x4 : CLK_DIV_4
IOCONCLKDIV4
0x5 : CLK_DIV_5
IOCONCLKDIV5
0x6 : CLK_DIV_6
IOCONCLKDIV6
End of enumeration elements list.
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