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IOCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PIO0_17

PIO0

PIO0_4

PIO4

PIO0_3

PIO5

PIO0_2

PIO6

PIO0_11

PIO7

PIO0_10

PIO8

PIO0_16

PIO9

PIO0_15

PIO10

PIO0_1

PIO11

PIO12

PIO0_9

PIO13

PIO0_8

PIO14

PIO0_7

PIO15

PIO0_13

PIO1

PIO0_6

PIO16

PIO0_0

PIO17

PIO0_14

PIO18

PIO19

PIO0_28

PIO20

PIO0_27

PIO21

PIO0_26

PIO22

PIO0_25

PIO23

PIO0_24

PIO24

PIO0_23

PIO25

PIO0_22

PIO26

PIO0_21

PIO27

PIO0_20

PIO28

PIO0_19

PIO29

PIO0_18

PIO30

PIO1_8

PIO31

PIO0_12

PIO2

PIO1_9

PIO32

PIO1_12

PIO33

PIO1_13

PIO34

PIO0_31

PIO35

PIO1_0

PIO36

PIO1_1

PIO37

PIO1_2

PIO38

PIO1_14

PIO39

PIO1_15

PIO40

PIO1_3

PIO41

PIO1_4

PIO42

PIO1_5

PIO43

PIO1_16

PIO44

PIO1_17

PIO45

PIO1_6

PIO46

PIO1_18

PIO47

PIO0_5

PIO3

PIO1_19

PIO48

PIO1_7

PIO49

PIO0_29

PIO50

PIO0_30

PIO51

PIO1_20

PIO52

PIO1_21

PIO53

PIO1_11

PIO54

PIO1_10

PIO55


PIO0_17

Digital I/O control for pins PIO0_17
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_17 PIO0_17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV DACMODE

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.

DACMODE : DAC mode enable.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLE

Enable.

End of enumeration elements list.


PIO0

Digital I/O control for port 0 pins PIO0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0 PIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV DACMODE

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.

DACMODE : DAC mode enable.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLE

Enable.

End of enumeration elements list.


PIO0_4

Digital I/O control for pins PIO0_4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_4 PIO0_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO4

Digital I/O control for port 0 pins PIO4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO4 PIO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_3

Digital I/O control for pins PIO0_3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_3 PIO0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO5

Digital I/O control for port 0 pins PIO5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO5 PIO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_2

Digital I/O control for pins PIO0_2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_2 PIO0_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO6

Digital I/O control for port 0 pins PIO6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO6 PIO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_11

Digital I/O control for pins PIO0_11
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_11 PIO0_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INV I2CMODE S_MODE CLK_DIV

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : STANDARAD_I2C

Standard mode/ Fast-mode I2C.

0x1 : Standard_GPIO

Standard GPIO functionality. Requires external pull-up for GPIO output function.

0x2 : FAST_PLUS_I2C

Fast-mode Plus I2C

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO7

Digital I/O control for port 0 pins PIO7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO7 PIO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INV I2CMODE S_MODE CLK_DIV

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : STANDARAD_I2C

Standard mode/ Fast-mode I2C.

0x1 : Standard_GPIO

Standard GPIO functionality. Requires external pull-up for GPIO output function.

0x2 : FAST_PLUS_I2C

Fast-mode Plus I2C

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_10

Digital I/O control for pins PIO0_10
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_10 PIO0_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INV I2CMODE S_MODE CLK_DIV

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : STANDARAD_I2C

Standard mode/ Fast-mode I2C.

0x1 : Standard_GPIO

Standard GPIO functionality. Requires external pull-up for GPIO output function.

0x2 : FAST_PLUS_I2C

Fast-mode Plus I2C

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO8

Digital I/O control for port 0 pins PIO8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO8 PIO8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INV I2CMODE S_MODE CLK_DIV

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

I2CMODE : Selects I2C mode.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : STANDARAD_I2C

Standard mode/ Fast-mode I2C.

0x1 : Standard_GPIO

Standard GPIO functionality. Requires external pull-up for GPIO output function.

0x2 : FAST_PLUS_I2C

Fast-mode Plus I2C

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_16

Digital I/O control for pins PIO0_16
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_16 PIO0_16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO9

Digital I/O control for port 0 pins PIO9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO9 PIO9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_15

Digital I/O control for pins PIO0_15
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_15 PIO0_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO10

Digital I/O control for port 0 pins PIO10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO10 PIO10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_1

Digital I/O control for pins PIO0_1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_1 PIO0_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO11

Digital I/O control for port 0 pins PIO11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO11 PIO11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO12

Digital I/O control for port 0 pins PIO12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO12 PIO12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_9

Digital I/O control for pins PIO0_9
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_9 PIO0_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO13

Digital I/O control for port 0 pins PIO13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO13 PIO13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_8

Digital I/O control for pins PIO0_8
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_8 PIO0_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO14

Digital I/O control for port 0 pins PIO14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO14 PIO14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_7

Digital I/O control for pins PIO0_7
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_7 PIO0_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO15

Digital I/O control for port 0 pins PIO15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO15 PIO15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_13

Digital I/O control for pins PIO0_13
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_13 PIO0_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1

Digital I/O control for port 0 pins PIO1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1 PIO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_6

Digital I/O control for pins PIO0_6
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_6 PIO0_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO16

Digital I/O control for port 0 pins PIO16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO16 PIO16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_0

Digital I/O control for pins PIO0_0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_0 PIO0_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO17

Digital I/O control for port 0 pins PIO17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO17 PIO17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_14

Digital I/O control for pins PIO0_14
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_14 PIO0_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO18

Digital I/O control for port 0 pins PIO18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO18 PIO18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO19

Digital I/O control for port 0 pins PIO19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO19 PIO19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_28

Digital I/O control for pins PIO0_28
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_28 PIO0_28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO20

Digital I/O control for port 0 pins PIO20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO20 PIO20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_27

Digital I/O control for pins PIO0_27
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_27 PIO0_27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO21

Digital I/O control for port 0 pins PIO21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO21 PIO21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_26

Digital I/O control for pins PIO0_26
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_26 PIO0_26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO22

Digital I/O control for port 0 pins PIO22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO22 PIO22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_25

Digital I/O control for pins PIO0_25
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_25 PIO0_25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO23

Digital I/O control for port 0 pins PIO23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO23 PIO23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_24

Digital I/O control for pins PIO0_24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_24 PIO0_24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO24

Digital I/O control for port 0 pins PIO24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO24 PIO24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_23

Digital I/O control for pins PIO0_23
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_23 PIO0_23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO25

Digital I/O control for port 0 pins PIO25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO25 PIO25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_22

Digital I/O control for pins PIO0_22
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_22 PIO0_22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO26

Digital I/O control for port 0 pins PIO26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO26 PIO26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_21

Digital I/O control for pins PIO0_21
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_21 PIO0_21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO27

Digital I/O control for port 0 pins PIO27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO27 PIO27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_20

Digital I/O control for pins PIO0_20
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_20 PIO0_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO28

Digital I/O control for port 0 pins PIO28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO28 PIO28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_19

Digital I/O control for pins PIO0_19
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_19 PIO0_19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO29

Digital I/O control for port 0 pins PIO29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO29 PIO29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_18

Digital I/O control for pins PIO0_18
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_18 PIO0_18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO30

Digital I/O control for port 0 pins PIO30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO30 PIO30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_8

Digital I/O control for pins PIO1_8
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_8 PIO1_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO31

Digital I/O control for port 0 pins PIO31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO31 PIO31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_12

Digital I/O control for pins PIO0_12
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_12 PIO0_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO2

Digital I/O control for port 0 pins PIO2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO2 PIO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_9

Digital I/O control for pins PIO1_9
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_9 PIO1_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO32

Digital I/O control for port 1 pins PIO32
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO32 PIO32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_12

Digital I/O control for pins PIO1_12
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_12 PIO1_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO33

Digital I/O control for port 1 pins PIO33
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO33 PIO33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_13

Digital I/O control for pins PIO1_13
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_13 PIO1_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO34

Digital I/O control for port 1 pins PIO34
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO34 PIO34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_31

Digital I/O control for pins PIO0_31
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_31 PIO0_31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO35

Digital I/O control for port 1 pins PIO35
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO35 PIO35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_0

Digital I/O control for pins PIO1_0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_0 PIO1_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO36

Digital I/O control for port 1 pins PIO36
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO36 PIO36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_1

Digital I/O control for pins PIO1_1
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_1 PIO1_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO37

Digital I/O control for port 1 pins PIO37
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO37 PIO37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_2

Digital I/O control for pins PIO1_2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_2 PIO1_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO38

Digital I/O control for port 1 pins PIO38
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO38 PIO38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_14

Digital I/O control for pins PIO1_14
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_14 PIO1_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO39

Digital I/O control for port 1 pins PIO39
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO39 PIO39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_15

Digital I/O control for pins PIO1_15
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_15 PIO1_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO40

Digital I/O control for port 1 pins PIO40
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO40 PIO40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_3

Digital I/O control for pins PIO1_3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_3 PIO1_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO41

Digital I/O control for port 1 pins PIO41
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO41 PIO41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_4

Digital I/O control for pins PIO1_4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_4 PIO1_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO42

Digital I/O control for port 1 pins PIO42
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO42 PIO42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_5

Digital I/O control for pins PIO1_5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_5 PIO1_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO43

Digital I/O control for port 1 pins PIO43
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO43 PIO43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_16

Digital I/O control for pins PIO1_16
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_16 PIO1_16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO44

Digital I/O control for port 1 pins PIO44
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO44 PIO44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_17

Digital I/O control for pins PIO1_17
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_17 PIO1_17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO45

Digital I/O control for port 1 pins PIO45
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO45 PIO45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_6

Digital I/O control for pins PIO1_6
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_6 PIO1_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO46

Digital I/O control for port 1 pins PIO46
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO46 PIO46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_18

Digital I/O control for pins PIO1_18
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_18 PIO1_18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO47

Digital I/O control for port 1 pins PIO47
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO47 PIO47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_5

Digital I/O control for pins PIO0_5
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_5 PIO0_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO3

Digital I/O control for port 0 pins PIO3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO3 PIO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_19

Digital I/O control for pins PIO1_19
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_19 PIO1_19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO48

Digital I/O control for port 1 pins PIO48
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO48 PIO48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_7

Digital I/O control for pins PIO1_7
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_7 PIO1_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO49

Digital I/O control for port 1 pins PIO49
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO49 PIO49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_29

Digital I/O control for pins PIO0_29
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_29 PIO0_29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO50

Digital I/O control for port 1 pins PIO50
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO50 PIO50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO0_30

Digital I/O control for pins PIO0_30
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO0_30 PIO0_30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO51

Digital I/O control for port 1 pins PIO51
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO51 PIO51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_20

Digital I/O control for pins PIO1_20
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_20 PIO1_20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO52

Digital I/O control for port 1 pins PIO52
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO52 PIO52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_21

Digital I/O control for pins PIO1_21
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_21 PIO1_21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO53

Digital I/O control for port 1 pins PIO53
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO53 PIO53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_11

Digital I/O control for pins PIO1_11
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_11 PIO1_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO54

Digital I/O control for port 1 pins PIO54
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO54 PIO54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO1_10

Digital I/O control for pins PIO1_10
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO1_10 PIO1_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.


PIO55

Digital I/O control for port 1 pins PIO55
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO55 PIO55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE HYS INV OD S_MODE CLK_DIV

MODE : Selects function mode (on-chip pull-up/pull-down resistor control).
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0 : INACTIVE

Inactive. Inactive (no pull-down/pull-up resistor enabled).

0x1 : PULL_DOWN

Pull-down. Pull-down resistor enabled.

0x2 : PULL_UP

Pull-up. Pull-up resistor enabled.

0x3 : REPEATER

Repeater. Repeater mode.

End of enumeration elements list.

HYS : Hysteresis.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable

0x1 : ENABLE

Enable

End of enumeration elements list.

INV : Invert input
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NOT_INVERTED

Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).

0x1 : INVERTED

Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).

End of enumeration elements list.

OD : Open-drain mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable.

0x1 : ENABLED

Open-drain mode enabled. Remark: This is not a true open-drain mode.

End of enumeration elements list.

S_MODE : Digital filter sample mode.
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : S_MODE_0

Bypass input filter.

0x1 : S_MODE_1

1 clock cycle. Input pulses shorter than one filter clock are rejected.

0x2 : S_MODE_2

2 clock cycles. Input pulses shorter than two filter clocks are rejected.

0x3 : S_MODE_3

3 clock cycles. Input pulses shorter than three filter clocks are rejected.

End of enumeration elements list.

CLK_DIV : Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

0 : CLK_DIV_0

IOCONCLKDIV0

0x1 : CLK_DIV_1

IOCONCLKDIV1

0x2 : CLK_DIV_2

IOCONCLKDIV2

0x3 : CLK_DIV_3

IOCONCLKDIV3

0x4 : CLK_DIV_4

IOCONCLKDIV4

0x5 : CLK_DIV_5

IOCONCLKDIV5

0x6 : CLK_DIV_6

IOCONCLKDIV6

End of enumeration elements list.



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